TY - GEN
T1 - Design of a 1.8V 6-bit 100MSPS 5mW CMOS A/D converter with low power folding-interpolation techniques
AU - Hwang, Sanghoon
AU - Moon, Junho
AU - Jung, Seunghwi
AU - Song, Minkyu
PY - 2006
Y1 - 2006
N2 - In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them, compared to the conventional ones. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93pJ/convstep. The active chip occupies an area of 0.28mm 2 in 0.18um CMOS technology.
AB - In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them, compared to the conventional ones. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93pJ/convstep. The active chip occupies an area of 0.28mm 2 in 0.18um CMOS technology.
UR - http://www.scopus.com/inward/record.url?scp=84865431097&partnerID=8YFLogxK
U2 - 10.1109/ESSCIR.2006.307511
DO - 10.1109/ESSCIR.2006.307511
M3 - Conference contribution
AN - SCOPUS:84865431097
SN - 1424403022
SN - 9781424403028
T3 - ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference
SP - 548
EP - 551
BT - ESSCIRC 2006 - Proceedings of the 32nd European Solid-State Circuits Conference
T2 - ESSCIRC 2006 - 32nd European Solid-State Circuits Conference
Y2 - 19 September 2006 through 21 September 2006
ER -