Design of a 1.8V 6-bit folding interpolation CMOS A/D converter with a 0.93[pJ/convstep] figure-of-merit

Sanghoon Hwang, Junho Moon, Minkyu Song

Research output: Contribution to journalArticlepeer-review

6 Scopus citations

Abstract

In this paper, a CMOS analog-to-digital converter (ADC)with a 6-bit 100 MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type with a resistive interpolation technique for low power consumption. To reduce the power consumption , a folder reduction technique to decrease the number of folding blocks (NFB) by half of the conventional ones, an averaging folder technique, and a compensated resistive interpolation technique are proposed. Further, an autoswitching encoder for efficient digital processing is also presented. With the clock speed of 100 MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50 MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FoM) is 0.93[pJ/convstep]. Theactive chip occupies an area of 0.28mm2 in 0.18μm CMOS technology.

Original languageEnglish
Pages (from-to)213-219
Number of pages7
JournalIEICE Transactions on Electronics
VolumeE91-C
Issue number2
DOIs
StatePublished - Feb 2008

Keywords

  • A/D converter
  • Averaging technique
  • Folding and interpolation architecture

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