TY - GEN
T1 - Design of a 1.8V 6bits low power F/I CMOS A/D converter with a novel folder-reduction technique
AU - Hwang, Sanghoon
AU - Song, Minkyu
PY - 2006
Y1 - 2006
N2 - In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them, compared to the conventional ones. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FOM) is 0.93pJ/convstep. The active chip occupies an area of 0.28mm2 in 0.18um CMOS technology.
AB - In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100MSPS at 1.8V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them, compared to the conventional ones. With the clock speed of 100MSPS, the ADC achieves an effective resolution bandwidth (ERBW) of 50MHz, while consuming only 4.5mW of power. The measured result of figure-of-merit (FOM) is 0.93pJ/convstep. The active chip occupies an area of 0.28mm2 in 0.18um CMOS technology.
UR - http://www.scopus.com/inward/record.url?scp=34547304977&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:34547304977
SN - 1424401577
SN - 9781424401574
T3 - PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics - Proceedings
SP - 285
EP - 288
BT - PRIME 2006
T2 - PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics
Y2 - 12 June 2006 through 15 June 2006
ER -