Design of a 1.8V 8-bit 1GSPS cascaded-folding CMOS A/D converter based on a folder averaging technique

Dongheon Lee; Seunghun Kim; Jooho Hwang; Junho Moon; Minkyu Song

doi:10.1109/SOCCON.2009.5398092

Design of a 1.8V 8-bit 1GSPS cascaded-folding CMOS A/D converter based on a folder averaging technique

Dongheon Lee
, Seunghun Kim
, Jooho Hwang
, Junho Moon
, Minkyu Song

Division of System Semiconductor

Dongguk University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 1GSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascaded-folding and an interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the highperformance are introduced. Further, a novel autoswitching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.72mm² and it consumes about 200mW at 1.8V power supply.

Original language	English
Title of host publication	Proceedings - IEEE International SOC Conference, SOCC 2009
Pages	79-82
Number of pages	4
DOIs	https://doi.org/10.1109/SOCCON.2009.5398092
State	Published - 2009
Event	IEEE International SOC Conference, SOCC 2009 - Belfast, Ireland Duration: 9 Sep 2009 → 11 Sep 2009

Publication series

Name	Proceedings - IEEE International SOC Conference, SOCC 2009

Conference

Conference	IEEE International SOC Conference, SOCC 2009
Country/Territory	Ireland
City	Belfast
Period	9/09/09 → 11/09/09

Access to Document

10.1109/SOCCON.2009.5398092

Cite this

@inproceedings{e997bb2730ee480a92fda15c3849ed69,

title = "Design of a 1.8V 8-bit 1GSPS cascaded-folding CMOS A/D converter based on a folder averaging technique",

abstract = "In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 1GSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascaded-folding and an interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the highperformance are introduced. Further, a novel autoswitching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.72mm2 and it consumes about 200mW at 1.8V power supply.",

author = "Dongheon Lee and Seunghun Kim and Jooho Hwang and Junho Moon and Minkyu Song",

year = "2009",

doi = "10.1109/SOCCON.2009.5398092",

language = "English",

isbn = "9781424452200",

series = "Proceedings - IEEE International SOC Conference, SOCC 2009",

pages = "79--82",

booktitle = "Proceedings - IEEE International SOC Conference, SOCC 2009",

note = "IEEE International SOC Conference, SOCC 2009 ; Conference date: 09-09-2009 Through 11-09-2009",

}

Lee, D, Kim, S, Hwang, J, Moon, J & Song, M 2009, Design of a 1.8V 8-bit 1GSPS cascaded-folding CMOS A/D converter based on a folder averaging technique. in Proceedings - IEEE International SOC Conference, SOCC 2009., 5398092, Proceedings - IEEE International SOC Conference, SOCC 2009, pp. 79-82, IEEE International SOC Conference, SOCC 2009, Belfast, Ireland, 9/09/09. https://doi.org/10.1109/SOCCON.2009.5398092

Design of a 1.8V 8-bit 1GSPS cascaded-folding CMOS A/D converter based on a folder averaging technique. / Lee, Dongheon; Kim, Seunghun; Hwang, Jooho et al.
Proceedings - IEEE International SOC Conference, SOCC 2009. 2009. p. 79-82 5398092 (Proceedings - IEEE International SOC Conference, SOCC 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Design of a 1.8V 8-bit 1GSPS cascaded-folding CMOS A/D converter based on a folder averaging technique

AU - Lee, Dongheon

AU - Kim, Seunghun

AU - Hwang, Jooho

AU - Moon, Junho

AU - Song, Minkyu

PY - 2009

Y1 - 2009

N2 - In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 1GSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascaded-folding and an interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the highperformance are introduced. Further, a novel autoswitching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.72mm2 and it consumes about 200mW at 1.8V power supply.

AB - In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 1GSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascaded-folding and an interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the highperformance are introduced. Further, a novel autoswitching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.72mm2 and it consumes about 200mW at 1.8V power supply.

UR - https://www.scopus.com/pages/publications/77949573530

U2 - 10.1109/SOCCON.2009.5398092

DO - 10.1109/SOCCON.2009.5398092

M3 - Conference contribution

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SN - 9781424452200

T3 - Proceedings - IEEE International SOC Conference, SOCC 2009

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BT - Proceedings - IEEE International SOC Conference, SOCC 2009

T2 - IEEE International SOC Conference, SOCC 2009

Y2 - 9 September 2009 through 11 September 2009

ER -

Design of a 1.8V 8-bit 1GSPS cascaded-folding CMOS A/D converter based on a folder averaging technique

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