@inproceedings{6282daf82f6647d88beae8ad7b395c2b,
title = "Design of a 1.8V 8-bit 500MSPS Folding-interpolation CMOS A/D converter with a folder averaging technique",
abstract = "In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 500MSPS at 1.8V is designed. The architecture of the proposed ADC is based on a Folding ADC with a cascaded-folding and a cascaded-interpolation structure. A self-linearized pre-amplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.79mm 2 and it consumes about 200mW at 1.8V power supply. The DNL and INL are within ±0.6/±0.6LSB, respectively. The measured result of SNDR is 47.05dB.",
author = "Dongjin Lee and Jaewon Song and Jongha Shin and Sanghoon Hwang and Minkyu Song and Tad Wysocki",
year = "2007",
doi = "10.1109/ECCTD.2007.4529606",
language = "English",
isbn = "1424413427",
series = "European Conference on Circuit Theory and Design 2007, ECCTD 2007",
publisher = "IEEE Computer Society",
pages = "356--359",
booktitle = "European Conference on Circuit Theory and Design 2007, ECCTD 2007",
address = "United States",
note = "European Conference on Circuit Theory and Design 2007, ECCTD 2007 ; Conference date: 26-08-2007 Through 30-08-2007",
}