@inproceedings{8595eb1d62d049e3a461775e2ea9f516,
title = "Design of a 45nm 8-bit 2GS/s 250mW CMOS folding A/D converter with an adaptive digital error correction technique",
abstract = "An 8-bit 2GS/s 250mW low power folding A/D converter(ADC) with a 45nm CMOS technology is described. In order to reduce the power consumption, a new folding block with a shut-down circuit is proposed. The role of shut-down circuit selectively cuts off the power supply of folding amplifiers, according to the input analog voltage. Further, an adaptive digital error correction technique is discussed to reduce the code errors. The proposed ADC has been fabricated with a 1.2V 45nm 1-poly 8-metal CMOS process. The effective chip area is 1.98mm2 (ADC core : 1.1mm2, Calibration : 0.88mm2) and the power consumption is about 250mW. The measured SNDR is 46dB at the conversion rate of 2GS/s. The measured values of INL and DNL are within 2.5LSB and 1.0 LSB, respectively.",
keywords = "a folding A/D Converter, a shut-down circuit, an adaptive digital error correction, measured SNDR",
author = "Yanghyuck Choi and Seonghyun Park and Lee, {Mun Kyo} and Nah, {Sun Phil} and Minkyu Song",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 12th International SoC Design Conference, ISOCC 2015 ; Conference date: 02-11-2015 Through 05-11-2015",
year = "2016",
month = feb,
day = "8",
doi = "10.1109/ISOCC.2015.7401640",
language = "English",
series = "ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "75--76",
booktitle = "ISOCC 2015 - International SoC Design Conference",
address = "United States",
}