Design of a 45nm 8-bit 2GS/s 250mW CMOS folding A/D converter with an adaptive digital error correction technique

Yanghyuck Choi, Seonghyun Park, Mun Kyo Lee, Sun Phil Nah, Minkyu Song

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

An 8-bit 2GS/s 250mW low power folding A/D converter(ADC) with a 45nm CMOS technology is described. In order to reduce the power consumption, a new folding block with a shut-down circuit is proposed. The role of shut-down circuit selectively cuts off the power supply of folding amplifiers, according to the input analog voltage. Further, an adaptive digital error correction technique is discussed to reduce the code errors. The proposed ADC has been fabricated with a 1.2V 45nm 1-poly 8-metal CMOS process. The effective chip area is 1.98mm2 (ADC core : 1.1mm2, Calibration : 0.88mm2) and the power consumption is about 250mW. The measured SNDR is 46dB at the conversion rate of 2GS/s. The measured values of INL and DNL are within 2.5LSB and 1.0 LSB, respectively.

Original languageEnglish
Title of host publicationISOCC 2015 - International SoC Design Conference
Subtitle of host publicationSoC for Internet of Everything (IoE)
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages75-76
Number of pages2
ISBN (Electronic)9781467393089
DOIs
StatePublished - 8 Feb 2016
Event12th International SoC Design Conference, ISOCC 2015 - Gyeongju, Korea, Republic of
Duration: 2 Nov 20155 Nov 2015

Publication series

NameISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)

Conference

Conference12th International SoC Design Conference, ISOCC 2015
Country/TerritoryKorea, Republic of
CityGyeongju
Period2/11/155/11/15

Keywords

  • a folding A/D Converter
  • a shut-down circuit
  • an adaptive digital error correction
  • measured SNDR

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