Design of a 6-bit IGSPS fully folded CMOS A/D converter for Ultra Wide Band (UWB) applications

Doobock Lee; Seungjin Yeo; Heewon Kang; Daeyoon Kim; Junho Moon; Minkyu Song

doi:10.1109/ICICDT.2008.4567258

Design of a 6-bit IGSPS fully folded CMOS A/D converter for Ultra Wide Band (UWB) applications

Doobock Lee, Seungjin Yeo, Heewon Kang, Daeyoon Kim, Junho Moon, Minkyu Song

Division of System Semiconductor

Dongguk University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

In this paper, a CMOS analog-to-digital converter (ADC) for Ultra Wide Band (UWB) applications with a 6-bit IGSPS at 1.8V is described. The architecture of the proposed ADC is based on a fully folded ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) is proposed. Further, a novel layout technique is introduced for compact area. With the clock speed of IGHz, the ADC achieves an effective resolution bandwidth (ERBW) of 200MHz, while consuming only 60mW of power. The measured INL and DNL are within ±0.7LSB, ±0.5LSB, respectively. The measured SNDR is 33.64dB, when F_in=100MHz at F_s=IGHz. The active chip occupies an area of 0.27mm² in 0.18μm CMOS technology.

Original language	English
Title of host publication	Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT
Pages	113-116
Number of pages	4
DOIs	https://doi.org/10.1109/ICICDT.2008.4567258
State	Published - 2008
Event	IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2008 - Minatec Grenoble, France Duration: 2 Jun 2008 → 4 Jun 2008

Publication series

Name	Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Conference

Conference	IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2008
Country/Territory	France
City	Minatec Grenoble
Period	2/06/08 → 4/06/08

Keywords

ADC
Folding/interpolation
Low power
UWB

Access to Document

10.1109/ICICDT.2008.4567258

Cite this

Lee, D., Yeo, S., Kang, H., Kim, D., Moon, J., & Song, M. (2008). Design of a 6-bit IGSPS fully folded CMOS A/D converter for Ultra Wide Band (UWB) applications. In Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT (pp. 113-116). Article 4567258 (Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT). https://doi.org/10.1109/ICICDT.2008.4567258

Lee, Doobock ; Yeo, Seungjin ; Kang, Heewon et al. / Design of a 6-bit IGSPS fully folded CMOS A/D converter for Ultra Wide Band (UWB) applications. Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT. 2008. pp. 113-116 (Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT).

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title = "Design of a 6-bit IGSPS fully folded CMOS A/D converter for Ultra Wide Band (UWB) applications",

abstract = "In this paper, a CMOS analog-to-digital converter (ADC) for Ultra Wide Band (UWB) applications with a 6-bit IGSPS at 1.8V is described. The architecture of the proposed ADC is based on a fully folded ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) is proposed. Further, a novel layout technique is introduced for compact area. With the clock speed of IGHz, the ADC achieves an effective resolution bandwidth (ERBW) of 200MHz, while consuming only 60mW of power. The measured INL and DNL are within ±0.7LSB, ±0.5LSB, respectively. The measured SNDR is 33.64dB, when Fin=100MHz at Fs=IGHz. The active chip occupies an area of 0.27mm2 in 0.18μm CMOS technology.",

keywords = "ADC, Folding/interpolation, Low power, UWB",

author = "Doobock Lee and Seungjin Yeo and Heewon Kang and Daeyoon Kim and Junho Moon and Minkyu Song",

year = "2008",

doi = "10.1109/ICICDT.2008.4567258",

language = "English",

isbn = "9781424418114",

series = "Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT",

pages = "113--116",

booktitle = "Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT",

note = "IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2008 ; Conference date: 02-06-2008 Through 04-06-2008",

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Lee, D, Yeo, S, Kang, H, Kim, D, Moon, J & Song, M 2008, Design of a 6-bit IGSPS fully folded CMOS A/D converter for Ultra Wide Band (UWB) applications. in Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT., 4567258, Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT, pp. 113-116, IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2008, Minatec Grenoble, France, 2/06/08. https://doi.org/10.1109/ICICDT.2008.4567258

Design of a 6-bit IGSPS fully folded CMOS A/D converter for Ultra Wide Band (UWB) applications. / Lee, Doobock; Yeo, Seungjin; Kang, Heewon et al.
Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT. 2008. p. 113-116 4567258 (Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Moon, Junho

AU - Song, Minkyu

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AB - In this paper, a CMOS analog-to-digital converter (ADC) for Ultra Wide Band (UWB) applications with a 6-bit IGSPS at 1.8V is described. The architecture of the proposed ADC is based on a fully folded ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) is proposed. Further, a novel layout technique is introduced for compact area. With the clock speed of IGHz, the ADC achieves an effective resolution bandwidth (ERBW) of 200MHz, while consuming only 60mW of power. The measured INL and DNL are within ±0.7LSB, ±0.5LSB, respectively. The measured SNDR is 33.64dB, when Fin=100MHz at Fs=IGHz. The active chip occupies an area of 0.27mm2 in 0.18μm CMOS technology.

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Lee D, Yeo S, Kang H, Kim D, Moon J, Song M. Design of a 6-bit IGSPS fully folded CMOS A/D converter for Ultra Wide Band (UWB) applications. In Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT. 2008. p. 113-116. 4567258. (Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT). doi: 10.1109/ICICDT.2008.4567258

Design of a 6-bit IGSPS fully folded CMOS A/D converter for Ultra Wide Band (UWB) applications

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