Design of a 9-bit 1GS/s CMOS folding A/D converter with a boundary error reduction technique

Jongyoon Hwang, Dongjoo Kim, Mun Kyo Lee, Sun Phil Nah, Minkyu Song

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper, design of a 9-bit 1GS/s CMOS folding A/D converter with a boundary error reduction technique is described. In order to reduce the asymmetrical boundary error of the folding ADCs, a new circuit is proposed. Further, an enhanced digital architecture is discussed to support the boundary error reduction technique. The fabricated ADC has a novel digital logic to minimize device mismatching and many errors. The chip has been implemented with 1.1V 45nm Samsung CMOS technology. The effective chip area is 2.99mm2 and the power dissipation is 120mW. The measured result of SNDR is 45.35dB, when the input frequency is 150MHz at the sampling frequency of 1GHz. The measured INL is within +5LSB/-3LSB and DNL is within +1.5LSB/-1LSB

Original languageEnglish
Title of host publicationInternational System on Chip Conference
EditorsKaijian Shi, Thomas Buchner, Danella Zhao, Ramalingam Sridhar
PublisherIEEE Computer Society
Pages83-87
Number of pages5
ISBN (Electronic)9781479933785
DOIs
StatePublished - 5 Nov 2014
Event27th IEEE International System on Chip Conference, SOCC 2014 - Las Vegas, United States
Duration: 2 Sep 20145 Sep 2014

Publication series

NameInternational System on Chip Conference
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Conference

Conference27th IEEE International System on Chip Conference, SOCC 2014
Country/TerritoryUnited States
CityLas Vegas
Period2/09/145/09/14

Keywords

  • boundary error reduction technique
  • CMOS folding ADC
  • enhanced digital architecture

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