@inproceedings{18e1581e9e9e4216b3ca3ce71b26e06d,
title = "Design of a 9-bit 1GS/s CMOS folding A/D converter with a boundary error reduction technique",
abstract = "In this paper, design of a 9-bit 1GS/s CMOS folding A/D converter with a boundary error reduction technique is described. In order to reduce the asymmetrical boundary error of the folding ADCs, a new circuit is proposed. Further, an enhanced digital architecture is discussed to support the boundary error reduction technique. The fabricated ADC has a novel digital logic to minimize device mismatching and many errors. The chip has been implemented with 1.1V 45nm Samsung CMOS technology. The effective chip area is 2.99mm2 and the power dissipation is 120mW. The measured result of SNDR is 45.35dB, when the input frequency is 150MHz at the sampling frequency of 1GHz. The measured INL is within +5LSB/-3LSB and DNL is within +1.5LSB/-1LSB",
keywords = "boundary error reduction technique, CMOS folding ADC, enhanced digital architecture",
author = "Jongyoon Hwang and Dongjoo Kim and Lee, {Mun Kyo} and Nah, {Sun Phil} and Minkyu Song",
note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 27th IEEE International System on Chip Conference, SOCC 2014 ; Conference date: 02-09-2014 Through 05-09-2014",
year = "2014",
month = nov,
day = "5",
doi = "10.1109/SOCC.2014.6948904",
language = "English",
series = "International System on Chip Conference",
publisher = "IEEE Computer Society",
pages = "83--87",
editor = "Kaijian Shi and Thomas Buchner and Danella Zhao and Ramalingam Sridhar",
booktitle = "International System on Chip Conference",
address = "United States",
}