TY - JOUR
T1 - Design of a CMOS image sensor based on a 10-bit two-step single-slope ADC
AU - Hwang, Yeonseong
AU - Song, Minkyu
PY - 2014
Y1 - 2014
N2 - In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA (320 × 240) resolution. The fabricated chip size is 5 mm × 3 mm, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.
AB - In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA (320 × 240) resolution. The fabricated chip size is 5 mm × 3 mm, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.
KW - CMOS image sensor
KW - Hybrid correlated double sampling
KW - Two-step single slope ADC
UR - http://www.scopus.com/inward/record.url?scp=84900009385&partnerID=8YFLogxK
U2 - 10.5573/JSTS.2014.14.2.246
DO - 10.5573/JSTS.2014.14.2.246
M3 - Article
AN - SCOPUS:84900009385
SN - 1598-1657
VL - 14
SP - 246
EP - 251
JO - Journal of Semiconductor Technology and Science
JF - Journal of Semiconductor Technology and Science
IS - 2
ER -