TY - GEN
T1 - Design of a CMOS image sensor with a 10-bit two-step single-slope A/D converter and a hybrid correlated double sampling
AU - Hwang, Yeonseong
AU - Lee, Seongjoo
AU - Song, Minkyu
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014
Y1 - 2014
N2 - In this paper, a low-noise CMOS Image Sensor (CIS) based on a 10-bit two-step Single Slope A/D Converter (SS-ADC) with Hybrid CDS is proposed. In order to reduce the pixel noise, a Hybrid Correlated Double Sampling (H-CDS) is discussed. With this technique, Column Fixed Pattern Noise (CFPN) is drastically reduced by about 55% or more, compared to that of analog CDS only. Furthermore, to overcome low conversion speed of SS-ADC , two-step SS-ADC is proposed. The conversion speed of proposed two-step SS-ADC is 5us, while that of the conventional SS-ADC is about 40us at 25MHz reference clock. The proposed CIS has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA (320x240) resolution. The fabricated chip size is 5mm x 3mm, and the power consumption is about 35mW at 3.3V supply voltage. The measured CFPN is 0.8LSB, and the frame rate is 220 frames/s.
AB - In this paper, a low-noise CMOS Image Sensor (CIS) based on a 10-bit two-step Single Slope A/D Converter (SS-ADC) with Hybrid CDS is proposed. In order to reduce the pixel noise, a Hybrid Correlated Double Sampling (H-CDS) is discussed. With this technique, Column Fixed Pattern Noise (CFPN) is drastically reduced by about 55% or more, compared to that of analog CDS only. Furthermore, to overcome low conversion speed of SS-ADC , two-step SS-ADC is proposed. The conversion speed of proposed two-step SS-ADC is 5us, while that of the conventional SS-ADC is about 40us at 25MHz reference clock. The proposed CIS has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA (320x240) resolution. The fabricated chip size is 5mm x 3mm, and the power consumption is about 35mW at 3.3V supply voltage. The measured CFPN is 0.8LSB, and the frame rate is 220 frames/s.
KW - Digital CDS
KW - Hybrid CDS
KW - Hybrid correlated double sampling
KW - SS-ADC
KW - Two-step single slope ADC
UR - https://www.scopus.com/pages/publications/84929378875
M3 - Conference contribution
AN - SCOPUS:84929378875
T3 - Conference Proceedings - 10th Conference on Ph. D. Research in Microelectronics and Electronics, PRIME 2014
BT - Conference Proceedings - 10th Conference on Ph. D. Research in Microelectronics and Electronics, PRIME 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 10th Conference on Ph. D. Research in Microelectronics and Electronics, PRIME 2014
Y2 - 29 June 2014 through 3 July 2014
ER -