Abstract
In this paper, a high performance 32 × 32-bit multiplier for a DSP core is proposed. The multiplier is composed of a block of Booth Encoder, a block of data compression, and a block of a 64-bit adder. In the block of Booth encoder, a conditional sign decision Booth encoder that reduces the gate delay and power consumption is proposed. In the block of data compression, 4-2 and 9-2 data compressors based on a novel compound logic are used for the efficient compressing of extra sign bit. In the block of 64-bit adder, an adaptive MUX-based conditional select adder with a separated carry generation block is proposed. The proposed 32 × 32-bit multiplier is designed by a full-custom method and there are about 28,000 transistors in an active area of 900 μm × 500 μm with 0.25 μm CMOS technology. From the experimental results, the multiplication time of the multiplier is about 3.2 ns at 2.5 V power supply, and it consumes about 50 mW at 100 MHz.
Original language | English |
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Pages (from-to) | 1709-1717 |
Number of pages | 9 |
Journal | IEICE Transactions on Electronics |
Volume | E85-C |
Issue number | 9 |
State | Published - 2002 |
Keywords
- 32 × 32-bit multiplier
- 64-bit conditional select adder
- 9-2 compressor
- Compound logic
- Conditional sign decision Booth encoder