TY - GEN
T1 - Design of a Feature Extracted CMOS Image Sensor with a Novel Integrator and a Configurable ADC
AU - Lee, Hohyeon
AU - Song, Minkyu
N1 - Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - Design of a feature extracted CMOS image sensor (CIS) with a new integrator and configurable analog-to-digital converter (ADC) is described. Since a feature extraction is normally executed at the digital block of image signal processor (ISP), an ISP must be connected to the end of CIS. Namely, the system of feature extraction has been normally based on two-chip solution with CIS and ISP. In case of simple feature extraction, however, the block of ISP can be eliminated, if a special working block could be inserted in the middle of CIS. In order to implement a feature extracted CIS, a new integrator to detect the codes of neighboring pixels is proposed. Further, a configurable 8-bit and 1-bit single-slope ADC is discussed. To verify the performance, a prototype of CIS has been fabricated with an 180nm CMOS technology. The number of pixel array is 1920 x 1380, and the frame rate is 60. The measured power consumption is only 9mW, and it is drastically reduced compared to other conventional ones.
AB - Design of a feature extracted CMOS image sensor (CIS) with a new integrator and configurable analog-to-digital converter (ADC) is described. Since a feature extraction is normally executed at the digital block of image signal processor (ISP), an ISP must be connected to the end of CIS. Namely, the system of feature extraction has been normally based on two-chip solution with CIS and ISP. In case of simple feature extraction, however, the block of ISP can be eliminated, if a special working block could be inserted in the middle of CIS. In order to implement a feature extracted CIS, a new integrator to detect the codes of neighboring pixels is proposed. Further, a configurable 8-bit and 1-bit single-slope ADC is discussed. To verify the performance, a prototype of CIS has been fabricated with an 180nm CMOS technology. The number of pixel array is 1920 x 1380, and the frame rate is 60. The measured power consumption is only 9mW, and it is drastically reduced compared to other conventional ones.
KW - 8-bit and 1-bit single slope ADC
KW - feature extracted CMOS image sensor
KW - image signal processor
KW - integrator circuit
UR - http://www.scopus.com/inward/record.url?scp=85146979616&partnerID=8YFLogxK
U2 - 10.1109/ICM56065.2022.10005511
DO - 10.1109/ICM56065.2022.10005511
M3 - Conference contribution
AN - SCOPUS:85146979616
T3 - 2022 International Conference on Microelectronics, ICM 2022
SP - 237
EP - 240
BT - 2022 International Conference on Microelectronics, ICM 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2022 International Conference on Microelectronics, ICM 2022
Y2 - 4 December 2022 through 7 December 2022
ER -