TY - GEN
T1 - Design of a high speed CMOS image sensor with a hybrid single-slope column ADC and a finite state machine
AU - Park, Keunyeol
AU - Jin, Minhyun
AU - Kim, Soo Youn
AU - Song, Minkyu
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2018/5/29
Y1 - 2018/5/29
N2 - In this paper, design of a CMOS Image sensor (CIS) with a hybrid single-slope ADC is presented. To obtain a small size and a high conversion rate CIS, no sampling capacitor structure is employed. This is implemented with a DC reference voltage and a single ramp generator. Further, by changing the input node of comparator, it reduces gain errors generated by a conventional 4-input comparator's differentia pair. The proposed hybrid ADC selects the resistor DAC's reference voltage controlled by a Finite State Machine(FSM), and converts the residual voltage with the single slope technique. Based on 1-Poly 5-Metal 90nm back side illuminated(BSI) CIS process, the chip satisfies 1920 × 1440 pixel resolution whose pitch is 1.4um and 1.75-Tr active pixel sensor(APS).
AB - In this paper, design of a CMOS Image sensor (CIS) with a hybrid single-slope ADC is presented. To obtain a small size and a high conversion rate CIS, no sampling capacitor structure is employed. This is implemented with a DC reference voltage and a single ramp generator. Further, by changing the input node of comparator, it reduces gain errors generated by a conventional 4-input comparator's differentia pair. The proposed hybrid ADC selects the resistor DAC's reference voltage controlled by a Finite State Machine(FSM), and converts the residual voltage with the single slope technique. Based on 1-Poly 5-Metal 90nm back side illuminated(BSI) CIS process, the chip satisfies 1920 × 1440 pixel resolution whose pitch is 1.4um and 1.75-Tr active pixel sensor(APS).
KW - 4-input comparator
KW - CMOS image sensor
KW - Finite state machine
KW - Hybrid single-slope column ADC
KW - Sampling capacitor
KW - Single ramp generator
UR - http://www.scopus.com/inward/record.url?scp=85048893951&partnerID=8YFLogxK
U2 - 10.1109/ISOCC.2017.8368786
DO - 10.1109/ISOCC.2017.8368786
M3 - Conference contribution
AN - SCOPUS:85048893951
T3 - Proceedings - International SoC Design Conference 2017, ISOCC 2017
SP - 95
EP - 96
BT - Proceedings - International SoC Design Conference 2017, ISOCC 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 14th International SoC Design Conference, ISOCC 2017
Y2 - 5 November 2017 through 8 November 2017
ER -