Design of a high speed CMOS image sensor with a hybrid single-slope column ADC and a finite state machine

Keunyeol Park, Minhyun Jin, Soo Youn Kim, Minkyu Song

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

In this paper, design of a CMOS Image sensor (CIS) with a hybrid single-slope ADC is presented. To obtain a small size and a high conversion rate CIS, no sampling capacitor structure is employed. This is implemented with a DC reference voltage and a single ramp generator. Further, by changing the input node of comparator, it reduces gain errors generated by a conventional 4-input comparator's differentia pair. The proposed hybrid ADC selects the resistor DAC's reference voltage controlled by a Finite State Machine(FSM), and converts the residual voltage with the single slope technique. Based on 1-Poly 5-Metal 90nm back side illuminated(BSI) CIS process, the chip satisfies 1920 × 1440 pixel resolution whose pitch is 1.4um and 1.75-Tr active pixel sensor(APS).

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2017, ISOCC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages95-96
Number of pages2
ISBN (Electronic)9781538622858
DOIs
StatePublished - 29 May 2018
Event14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of
Duration: 5 Nov 20178 Nov 2017

Publication series

NameProceedings - International SoC Design Conference 2017, ISOCC 2017

Conference

Conference14th International SoC Design Conference, ISOCC 2017
Country/TerritoryKorea, Republic of
CitySeoul
Period5/11/178/11/17

Keywords

  • 4-input comparator
  • CMOS image sensor
  • Finite state machine
  • Hybrid single-slope column ADC
  • Sampling capacitor
  • Single ramp generator

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