Design of a hybrid column segmented CMOS Image sensor with an artificial intelligence core and a novel SRAM readout logic

Keunyeol Park, Cheeyoung Lee, Soo Youn Kim, Minkyu Song

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, a hybrid column segmented CMOS image sensor (CIS) with an artificial intelligence (AI) core and a novel SRAM readout circuit is presented. To obtain a high performance and high speed column parallel CIS, each column is segmented into two parts: the first one is a DC reference voltage generator with a bandgap reference circuit, and the second one is a fine ramp generator with an AI core and a digital-to-analog converter (DAC). Further, a novel SRAM readout circuit to improve the speed of digital block is also discussed. Based on this hybrid column segmented technique, excellent measured results are reported. With a 90nm backside illumination (BSI) technology, a 12-bit resolution image quality and 407uW power consumption per column are satisfied.

Original languageEnglish
Title of host publicationICEIC 2019 - International Conference on Electronics, Information, and Communication
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9788995004449
DOIs
StatePublished - 3 May 2019
Event18th International Conference on Electronics, Information, and Communication, ICEIC 2019 - Auckland, New Zealand
Duration: 22 Jan 201925 Jan 2019

Publication series

NameICEIC 2019 - International Conference on Electronics, Information, and Communication

Conference

Conference18th International Conference on Electronics, Information, and Communication, ICEIC 2019
Country/TerritoryNew Zealand
CityAuckland
Period22/01/1925/01/19

Keywords

  • Artificial intelligence core
  • CMOS image sensor
  • Hybrid column segmented
  • SRAM readout logic

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