Design of a low power 10-bit cyclic D/A converter with a Johnson counter and a capacitor swapping technique

Hyosang Kim; Seunghoon Kim; Hyukbin Kwon; Junho Moon; Minkyu Song

doi:10.1109/NEWCAS.2009.5290476

Design of a low power 10-bit cyclic D/A converter with a Johnson counter and a capacitor swapping technique

Hyosang Kim, Seunghoon Kim, Hyukbin Kwon, Junho Moon, Minkyu Song

Division of System Semiconductor

Dongguk University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

A cyclic 10-bit D/A converter based on a Johnson counter and a capacitor swapping technique is described. To reduce capacitor mismatching errors, two capacitors are alternately swapped according to input data. Further, a half differential architecture to reduce offset errors and a Johnson counter to improve the digital logic performance are proposed. With a 0.35pm Samsung CMOS technology, the measured SFDR is about 65dB, when the input frequency is IMHz at a clock frequency of 2MHz. The power consumption is only 31OpW at 3.3V power supply. The measured INL and DNL are within ±0.7LSB and ±0.75LSB, respectively.

Original language	English
Title of host publication	2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09
DOIs	https://doi.org/10.1109/NEWCAS.2009.5290476
State	Published - 2009
Event	2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09 - Toulouse, France Duration: 28 Jun 2009 → 1 Jul 2009

Publication series

Name	2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09

Conference

Conference	2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09
Country/Territory	France
City	Toulouse
Period	28/06/09 → 1/07/09

Access to Document

10.1109/NEWCAS.2009.5290476

Cite this

Kim, H., Kim, S., Kwon, H., Moon, J., & Song, M. (2009). Design of a low power 10-bit cyclic D/A converter with a Johnson counter and a capacitor swapping technique. In 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09 Article 5290476 (2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09). https://doi.org/10.1109/NEWCAS.2009.5290476

Kim, Hyosang ; Kim, Seunghoon ; Kwon, Hyukbin et al. / Design of a low power 10-bit cyclic D/A converter with a Johnson counter and a capacitor swapping technique. 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09. 2009. (2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09).

@inproceedings{b605923b3855436f84917e833138730a,

title = "Design of a low power 10-bit cyclic D/A converter with a Johnson counter and a capacitor swapping technique",

abstract = "A cyclic 10-bit D/A converter based on a Johnson counter and a capacitor swapping technique is described. To reduce capacitor mismatching errors, two capacitors are alternately swapped according to input data. Further, a half differential architecture to reduce offset errors and a Johnson counter to improve the digital logic performance are proposed. With a 0.35pm Samsung CMOS technology, the measured SFDR is about 65dB, when the input frequency is IMHz at a clock frequency of 2MHz. The power consumption is only 31OpW at 3.3V power supply. The measured INL and DNL are within ±0.7LSB and ±0.75LSB, respectively.",

author = "Hyosang Kim and Seunghoon Kim and Hyukbin Kwon and Junho Moon and Minkyu Song",

year = "2009",

doi = "10.1109/NEWCAS.2009.5290476",

language = "English",

isbn = "9781424445738",

series = "2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09",

booktitle = "2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09",

note = "2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09 ; Conference date: 28-06-2009 Through 01-07-2009",

}

Kim, H, Kim, S, Kwon, H, Moon, J & Song, M 2009, Design of a low power 10-bit cyclic D/A converter with a Johnson counter and a capacitor swapping technique. in 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09., 5290476, 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09, 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09, Toulouse, France, 28/06/09. https://doi.org/10.1109/NEWCAS.2009.5290476

Design of a low power 10-bit cyclic D/A converter with a Johnson counter and a capacitor swapping technique. / Kim, Hyosang; Kim, Seunghoon; Kwon, Hyukbin et al.
2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09. 2009. 5290476 (2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - A cyclic 10-bit D/A converter based on a Johnson counter and a capacitor swapping technique is described. To reduce capacitor mismatching errors, two capacitors are alternately swapped according to input data. Further, a half differential architecture to reduce offset errors and a Johnson counter to improve the digital logic performance are proposed. With a 0.35pm Samsung CMOS technology, the measured SFDR is about 65dB, when the input frequency is IMHz at a clock frequency of 2MHz. The power consumption is only 31OpW at 3.3V power supply. The measured INL and DNL are within ±0.7LSB and ±0.75LSB, respectively.

AB - A cyclic 10-bit D/A converter based on a Johnson counter and a capacitor swapping technique is described. To reduce capacitor mismatching errors, two capacitors are alternately swapped according to input data. Further, a half differential architecture to reduce offset errors and a Johnson counter to improve the digital logic performance are proposed. With a 0.35pm Samsung CMOS technology, the measured SFDR is about 65dB, when the input frequency is IMHz at a clock frequency of 2MHz. The power consumption is only 31OpW at 3.3V power supply. The measured INL and DNL are within ±0.7LSB and ±0.75LSB, respectively.

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BT - 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09

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Kim H, Kim S, Kwon H, Moon J, Song M. Design of a low power 10-bit cyclic D/A converter with a Johnson counter and a capacitor swapping technique. In 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09. 2009. 5290476. (2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA '09). doi: 10.1109/NEWCAS.2009.5290476

Design of a low power 10-bit cyclic D/A converter with a Johnson counter and a capacitor swapping technique

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