Design of a low power 54×54-bit multiplier based on a pass-transistor logic

In this paper, a pass-transistor logic with an efficient level restoration circuit is proposed. It is shown how, through the use of regenerative feedback with pMOS switches, we reduce the power consumption and propagation delay compared to conventional pass-transistor logic. To demonstrate the performance of the proposed pass-transistor logic, a 54×54-bit multiplier is designed. For speed and power optimization, the multiplier uses high compression-rate compressors without Booth Encoding, and a 108-bit conditional sum adder with separated carry generation block. The measured multiplication time was 13.5 ns in a 0.6 μm single-poly triple-metal 3.3V CMOS process.