Design of a low power 54×54-bit multiplier based on a pass-transistor logic

Minkyu Song

doi:10.1109/ICECS.1998.814821

Design of a low power 54×54-bit multiplier based on a pass-transistor logic

Minkyu Song

Division of System Semiconductor

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

In this paper, a pass-transistor logic with an efficient level restoration circuit is proposed. It is shown how, through the use of regenerative feedback with pMOS switches, we reduce the power consumption and propagation delay compared to conventional pass-transistor logic. To demonstrate the performance of the proposed pass-transistor logic, a 54×54-bit multiplier is designed. For speed and power optimization, the multiplier uses high compression-rate compressors without Booth encoding, and a 108-bit conditional sum adder with separated carry generation block. The measured multiplication time was 13.5 ns in a 0.6 μm single-poly triple-metal 3.3 V CMOS process.

Original language	English
Title of host publication	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	51-56
Number of pages	6
ISBN (Electronic)	0780350081
DOIs	https://doi.org/10.1109/ICECS.1998.814821
State	Published - 1998
Event	5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998 - Lisboa, Portugal Duration: 7 Sep 1998 → 10 Sep 1998

Publication series

Name	Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume	2

Conference

Conference	5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998
Country/Territory	Portugal
City	Lisboa
Period	7/09/98 → 10/09/98

Access to Document

10.1109/ICECS.1998.814821

Cite this

Song, M. (1998). Design of a low power 54×54-bit multiplier based on a pass-transistor logic. In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (pp. 51-56). Article 814821 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.1998.814821

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title = "Design of a low power 54×54-bit multiplier based on a pass-transistor logic",

abstract = "In this paper, a pass-transistor logic with an efficient level restoration circuit is proposed. It is shown how, through the use of regenerative feedback with pMOS switches, we reduce the power consumption and propagation delay compared to conventional pass-transistor logic. To demonstrate the performance of the proposed pass-transistor logic, a 54×54-bit multiplier is designed. For speed and power optimization, the multiplier uses high compression-rate compressors without Booth encoding, and a 108-bit conditional sum adder with separated carry generation block. The measured multiplication time was 13.5 ns in a 0.6 μm single-poly triple-metal 3.3 V CMOS process.",

author = "Minkyu Song",

note = "Publisher Copyright: {\textcopyright} 1998 IEEE.; 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998 ; Conference date: 07-09-1998 Through 10-09-1998",

year = "1998",

doi = "10.1109/ICECS.1998.814821",

language = "English",

series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "51--56",

booktitle = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",

address = "United States",

}

Song, M 1998, Design of a low power 54×54-bit multiplier based on a pass-transistor logic. in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems., 814821, Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 2, Institute of Electrical and Electronics Engineers Inc., pp. 51-56, 5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Lisboa, Portugal, 7/09/98. https://doi.org/10.1109/ICECS.1998.814821

Design of a low power 54×54-bit multiplier based on a pass-transistor logic. / Song, Minkyu.
Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems. Institute of Electrical and Electronics Engineers Inc., 1998. p. 51-56 814821 (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, a pass-transistor logic with an efficient level restoration circuit is proposed. It is shown how, through the use of regenerative feedback with pMOS switches, we reduce the power consumption and propagation delay compared to conventional pass-transistor logic. To demonstrate the performance of the proposed pass-transistor logic, a 54×54-bit multiplier is designed. For speed and power optimization, the multiplier uses high compression-rate compressors without Booth encoding, and a 108-bit conditional sum adder with separated carry generation block. The measured multiplication time was 13.5 ns in a 0.6 μm single-poly triple-metal 3.3 V CMOS process.

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Song M. Design of a low power 54×54-bit multiplier based on a pass-transistor logic. In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems. Institute of Electrical and Electronics Engineers Inc. 1998. p. 51-56. 814821. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems). doi: 10.1109/ICECS.1998.814821

Design of a low power 54×54-bit multiplier based on a pass-transistor logic

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