Abstract
Energy Economized Pass-transistor Logic (EEPL) is proposed. Adopting the principle of regenerative positive feedback with pMOS switches, we reduce the power in comparison with CPL and SRPL. To demonstrate the performance of EEPL, a low power 7-bit serial counter is designed. The operating speed is about 250 MHz with 0.6 μm 3.3 V CMOS process.
Original language | English |
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Pages | 1033-1036 |
Number of pages | 4 |
State | Published - 1996 |
Event | Proceedings of the 1996 3rd IEEE International Conference on Electronics, Circuits, and Systems, ICECS. Part 2 (of 2) - Rodos, Greece Duration: 13 Oct 1996 → 16 Oct 1996 |
Conference
Conference | Proceedings of the 1996 3rd IEEE International Conference on Electronics, Circuits, and Systems, ICECS. Part 2 (of 2) |
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City | Rodos, Greece |
Period | 13/10/96 → 16/10/96 |