Design of a low power 7-bit serial counter with energy economized pass-transistor logic (EEPL)

Minkyu Song, Geunsoon Kang, Seongwon Kim, Euro Joe, Bongsoon Kang

Research output: Contribution to conferencePaperpeer-review

3 Scopus citations

Abstract

Energy Economized Pass-transistor Logic (EEPL) is proposed. Adopting the principle of regenerative positive feedback with pMOS switches, we reduce the power in comparison with CPL and SRPL. To demonstrate the performance of EEPL, a low power 7-bit serial counter is designed. The operating speed is about 250 MHz with 0.6 μm 3.3 V CMOS process.

Original languageEnglish
Pages1033-1036
Number of pages4
StatePublished - 1996
EventProceedings of the 1996 3rd IEEE International Conference on Electronics, Circuits, and Systems, ICECS. Part 2 (of 2) - Rodos, Greece
Duration: 13 Oct 199616 Oct 1996

Conference

ConferenceProceedings of the 1996 3rd IEEE International Conference on Electronics, Circuits, and Systems, ICECS. Part 2 (of 2)
CityRodos, Greece
Period13/10/9616/10/96

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