Design of a low power 7-bit serial counter with energy economized pass-transistor logic (EEPL)

Minkyu Song; Geunsoon Kang; Seongwon Kim; Euro Joe; Bongsoon Kang

Design of a low power 7-bit serial counter with energy economized pass-transistor logic (EEPL)

Minkyu Song
, Geunsoon Kang
, Seongwon Kim
, Euro Joe
, Bongsoon Kang

Division of System Semiconductor

Samsung

Research output: Contribution to conference › Paper › peer-review

3 Scopus citations

Abstract

Energy Economized Pass-transistor Logic (EEPL) is proposed. Adopting the principle of regenerative positive feedback with pMOS switches, we reduce the power in comparison with CPL and SRPL. To demonstrate the performance of EEPL, a low power 7-bit serial counter is designed. The operating speed is about 250 MHz with 0.6 μm 3.3 V CMOS process.

Original language	English
Pages	1033-1036
Number of pages	4
State	Published - 1996
Event	Proceedings of the 1996 3rd IEEE International Conference on Electronics, Circuits, and Systems, ICECS. Part 2 (of 2) - Rodos, Greece Duration: 13 Oct 1996 → 16 Oct 1996

Conference

Conference	Proceedings of the 1996 3rd IEEE International Conference on Electronics, Circuits, and Systems, ICECS. Part 2 (of 2)
City	Rodos, Greece
Period	13/10/96 → 16/10/96

Cite this

@conference{d0a15ce89b8144308fceeeb0fc42f210,

title = "Design of a low power 7-bit serial counter with energy economized pass-transistor logic (EEPL)",

abstract = "Energy Economized Pass-transistor Logic (EEPL) is proposed. Adopting the principle of regenerative positive feedback with pMOS switches, we reduce the power in comparison with CPL and SRPL. To demonstrate the performance of EEPL, a low power 7-bit serial counter is designed. The operating speed is about 250 MHz with 0.6 μm 3.3 V CMOS process.",

author = "Minkyu Song and Geunsoon Kang and Seongwon Kim and Euro Joe and Bongsoon Kang",

year = "1996",

language = "English",

pages = "1033--1036",

note = "Proceedings of the 1996 3rd IEEE International Conference on Electronics, Circuits, and Systems, ICECS. Part 2 (of 2) ; Conference date: 13-10-1996 Through 16-10-1996",

}

Design of a low power 7-bit serial counter with energy economized pass-transistor logic (EEPL). / Song, Minkyu; Kang, Geunsoon; Kim, Seongwon et al.
1996. 1033-1036 Paper presented at Proceedings of the 1996 3rd IEEE International Conference on Electronics, Circuits, and Systems, ICECS. Part 2 (of 2), Rodos, Greece.

Research output: Contribution to conference › Paper › peer-review

TY - CONF

T1 - Design of a low power 7-bit serial counter with energy economized pass-transistor logic (EEPL)

AU - Song, Minkyu

AU - Kang, Geunsoon

AU - Kim, Seongwon

AU - Joe, Euro

AU - Kang, Bongsoon

PY - 1996

Y1 - 1996

N2 - Energy Economized Pass-transistor Logic (EEPL) is proposed. Adopting the principle of regenerative positive feedback with pMOS switches, we reduce the power in comparison with CPL and SRPL. To demonstrate the performance of EEPL, a low power 7-bit serial counter is designed. The operating speed is about 250 MHz with 0.6 μm 3.3 V CMOS process.

AB - Energy Economized Pass-transistor Logic (EEPL) is proposed. Adopting the principle of regenerative positive feedback with pMOS switches, we reduce the power in comparison with CPL and SRPL. To demonstrate the performance of EEPL, a low power 7-bit serial counter is designed. The operating speed is about 250 MHz with 0.6 μm 3.3 V CMOS process.

UR - https://www.scopus.com/pages/publications/0030372972

M3 - Paper

AN - SCOPUS:0030372972

SP - 1033

EP - 1036

T2 - Proceedings of the 1996 3rd IEEE International Conference on Electronics, Circuits, and Systems, ICECS. Part 2 (of 2)

Y2 - 13 October 1996 through 16 October 1996

ER -

Design of a low power 7-bit serial counter with energy economized pass-transistor logic (EEPL)

Abstract

Conference

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