Abstract
A parallel structured 54 × 54 bit multiplier with low power data compressors is proposed. Using a tally-function circuit [1], an optimized low power data compressor is designed. The average power consumption of the proposed data compressor is reduced by about 35%, compared with that of the conventional multiplier [2]; while the propagation delay is nearly same as that of the conventional one.
| Original language | English |
|---|---|
| Pages | 775-777 |
| Number of pages | 3 |
| State | Published - 1995 |
| Event | Proceedings of the 1995 4th International Conference on Solid-State and Integrated Circuit Technology - Beijing, China Duration: 24 Oct 1995 → 28 Oct 1995 |
Conference
| Conference | Proceedings of the 1995 4th International Conference on Solid-State and Integrated Circuit Technology |
|---|---|
| City | Beijing, China |
| Period | 24/10/95 → 28/10/95 |