Design of a multiplier with low power data compressors

Minkyu Song

Design of a multiplier with low power data compressors

Minkyu Song

Division of System Semiconductor

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

A parallel structured 54 × 54 bit multiplier with low power data compressors is proposed. Using a tally-function circuit [1], an optimized low power data compressor is designed. The average power consumption of the proposed data compressor is reduced by about 35%, compared with that of the conventional multiplier [2]; while the propagation delay is nearly same as that of the conventional one.

Original language	English
Pages	775-777
Number of pages	3
State	Published - 1995
Event	Proceedings of the 1995 4th International Conference on Solid-State and Integrated Circuit Technology - Beijing, China Duration: 24 Oct 1995 → 28 Oct 1995

Conference

Conference	Proceedings of the 1995 4th International Conference on Solid-State and Integrated Circuit Technology
City	Beijing, China
Period	24/10/95 → 28/10/95

Cite this

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title = "Design of a multiplier with low power data compressors",

abstract = "A parallel structured 54 × 54 bit multiplier with low power data compressors is proposed. Using a tally-function circuit [1], an optimized low power data compressor is designed. The average power consumption of the proposed data compressor is reduced by about 35\%, compared with that of the conventional multiplier [2]; while the propagation delay is nearly same as that of the conventional one.",

author = "Minkyu Song",

year = "1995",

language = "English",

pages = "775--777",

note = "Proceedings of the 1995 4th International Conference on Solid-State and Integrated Circuit Technology ; Conference date: 24-10-1995 Through 28-10-1995",

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TY - CONF

T1 - Design of a multiplier with low power data compressors

AU - Song, Minkyu

PY - 1995

Y1 - 1995

N2 - A parallel structured 54 × 54 bit multiplier with low power data compressors is proposed. Using a tally-function circuit [1], an optimized low power data compressor is designed. The average power consumption of the proposed data compressor is reduced by about 35%, compared with that of the conventional multiplier [2]; while the propagation delay is nearly same as that of the conventional one.

AB - A parallel structured 54 × 54 bit multiplier with low power data compressors is proposed. Using a tally-function circuit [1], an optimized low power data compressor is designed. The average power consumption of the proposed data compressor is reduced by about 35%, compared with that of the conventional multiplier [2]; while the propagation delay is nearly same as that of the conventional one.

UR - https://www.scopus.com/pages/publications/0029458031

M3 - Paper

AN - SCOPUS:0029458031

SP - 775

EP - 777

T2 - Proceedings of the 1995 4th International Conference on Solid-State and Integrated Circuit Technology

Y2 - 24 October 1995 through 28 October 1995

ER -

Design of a multiplier with low power data compressors

Abstract

Conference

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