Design of a novel 3.3 v CMOS logarithmic amplifier with a two step linear limiting architecture

Sooyeon Kim; Minkyu Song

doi:10.1109/APCCAS.2002.1114922

Design of a novel 3.3 v CMOS logarithmic amplifier with a two step linear limiting architecture

Division of System Semiconductor

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

In this paper, we discuss the VLSI design of a logarithmic amplifier (LA) for wide dynamic range and high sensitivity radar systems. In general, an LA consists of an input stage, a logarithmic stage, and an output stage. In order to give a much wider dynamic range and a higher speed than the conventional LA, a new type of two-step linear limiting architecture is proposed in the logarithmic stage. Two kinds of simple attenuators, designed with resistors, and a 30 dB middle amplifier are inserted in the middle of the proposed architecture to reduce the complexity and to increase the input dynamic range. It is fabricated on the basis of 0.35 μm standard CMOS technology. The effective chip area is 1310 μm x 1540 μm, and shows a power consumption of 90 mW at 3.3 V supply voltage. Through simulation and measurements, it is verified that it shows the characteristics of 72 dB dynamic range and 50 ns pulse response.

Original language	English
Title of host publication	Proceedings - APCCAS 2002
Subtitle of host publication	Asia-Pacific Conference on Circuits and Systems
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	131-134
Number of pages	4
ISBN (Electronic)	0780376900
DOIs	https://doi.org/10.1109/APCCAS.2002.1114922
State	Published - 2002
Event	Asia-Pacific Conference on Circuits and Systems, APCCAS 2002 - Denpasar, Bali, Indonesia Duration: 28 Oct 2002 → 31 Oct 2002

Publication series

Name	IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Volume	1

Conference

Conference	Asia-Pacific Conference on Circuits and Systems, APCCAS 2002
Country/Territory	Indonesia
City	Denpasar, Bali
Period	28/10/02 → 31/10/02

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Attenuators
CMOS technology
Dynamic range
Energy consumption
Pulse measurements
Radar
Resistors
Semiconductor device measurement
Very large scale integration
Voltage

Access to Document

10.1109/APCCAS.2002.1114922

Cite this

Kim, S., & Song, M. (2002). Design of a novel 3.3 v CMOS logarithmic amplifier with a two step linear limiting architecture. In Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems (pp. 131-134). Article 1114922 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2002.1114922

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title = "Design of a novel 3.3 v CMOS logarithmic amplifier with a two step linear limiting architecture",

abstract = "In this paper, we discuss the VLSI design of a logarithmic amplifier (LA) for wide dynamic range and high sensitivity radar systems. In general, an LA consists of an input stage, a logarithmic stage, and an output stage. In order to give a much wider dynamic range and a higher speed than the conventional LA, a new type of two-step linear limiting architecture is proposed in the logarithmic stage. Two kinds of simple attenuators, designed with resistors, and a 30 dB middle amplifier are inserted in the middle of the proposed architecture to reduce the complexity and to increase the input dynamic range. It is fabricated on the basis of 0.35 μm standard CMOS technology. The effective chip area is 1310 μm x 1540 μm, and shows a power consumption of 90 mW at 3.3 V supply voltage. Through simulation and measurements, it is verified that it shows the characteristics of 72 dB dynamic range and 50 ns pulse response.",

keywords = "Attenuators, CMOS technology, Dynamic range, Energy consumption, Pulse measurements, Radar, Resistors, Semiconductor device measurement, Very large scale integration, Voltage",

author = "Sooyeon Kim and Minkyu Song",

note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; Asia-Pacific Conference on Circuits and Systems, APCCAS 2002 ; Conference date: 28-10-2002 Through 31-10-2002",

year = "2002",

doi = "10.1109/APCCAS.2002.1114922",

language = "English",

series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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}

Kim, S & Song, M 2002, Design of a novel 3.3 v CMOS logarithmic amplifier with a two step linear limiting architecture. in Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems., 1114922, IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, vol. 1, Institute of Electrical and Electronics Engineers Inc., pp. 131-134, Asia-Pacific Conference on Circuits and Systems, APCCAS 2002, Denpasar, Bali, Indonesia, 28/10/02. https://doi.org/10.1109/APCCAS.2002.1114922

Design of a novel 3.3 v CMOS logarithmic amplifier with a two step linear limiting architecture. / Kim, Sooyeon ; Song, Minkyu.
Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., 2002. p. 131-134 1114922 (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Kim, Sooyeon

AU - Song, Minkyu

PY - 2002

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N2 - In this paper, we discuss the VLSI design of a logarithmic amplifier (LA) for wide dynamic range and high sensitivity radar systems. In general, an LA consists of an input stage, a logarithmic stage, and an output stage. In order to give a much wider dynamic range and a higher speed than the conventional LA, a new type of two-step linear limiting architecture is proposed in the logarithmic stage. Two kinds of simple attenuators, designed with resistors, and a 30 dB middle amplifier are inserted in the middle of the proposed architecture to reduce the complexity and to increase the input dynamic range. It is fabricated on the basis of 0.35 μm standard CMOS technology. The effective chip area is 1310 μm x 1540 μm, and shows a power consumption of 90 mW at 3.3 V supply voltage. Through simulation and measurements, it is verified that it shows the characteristics of 72 dB dynamic range and 50 ns pulse response.

AB - In this paper, we discuss the VLSI design of a logarithmic amplifier (LA) for wide dynamic range and high sensitivity radar systems. In general, an LA consists of an input stage, a logarithmic stage, and an output stage. In order to give a much wider dynamic range and a higher speed than the conventional LA, a new type of two-step linear limiting architecture is proposed in the logarithmic stage. Two kinds of simple attenuators, designed with resistors, and a 30 dB middle amplifier are inserted in the middle of the proposed architecture to reduce the complexity and to increase the input dynamic range. It is fabricated on the basis of 0.35 μm standard CMOS technology. The effective chip area is 1310 μm x 1540 μm, and shows a power consumption of 90 mW at 3.3 V supply voltage. Through simulation and measurements, it is verified that it shows the characteristics of 72 dB dynamic range and 50 ns pulse response.

KW - Attenuators

KW - CMOS technology

KW - Dynamic range

KW - Energy consumption

KW - Pulse measurements

KW - Radar

KW - Resistors

KW - Semiconductor device measurement

KW - Very large scale integration

KW - Voltage

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BT - Proceedings - APCCAS 2002

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Kim S , Song M. Design of a novel 3.3 v CMOS logarithmic amplifier with a two step linear limiting architecture. In Proceedings - APCCAS 2002: Asia-Pacific Conference on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc. 2002. p. 131-134. 1114922. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS). doi: 10.1109/APCCAS.2002.1114922

Design of a novel 3.3 v CMOS logarithmic amplifier with a two step linear limiting architecture

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

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