TY - GEN
T1 - Design of a small area and low power CMOS D/A converter based on the alpha-power law MOSFET model
AU - Kim, Daeyoon
AU - Hwang, Sanghoon
AU - Kang, Heewon
AU - Yeo, Seungjin
AU - Lee, Dubok
AU - Moon, Junho
AU - Song, Minkyu
PY - 2008
Y1 - 2008
N2 - While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the Alpha-Power Law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockley's square model. In this paper, we describe a 6-b 100MSPS CMOS current steering Digital-to-Analog Converter (DAC) with the Alpha-Power Law model. In order to improve the matching characteristics of the DAC current cell, moreover, we introduce a new and unique adaptive-control- switch (ACS) and a common current cell layout technique using a tournament algorithm. The prototype circuit has been fabricated with a Samsung 1.8V, 0.18μm, 1-poly, 5-metal CMOS technology. It occupies 0.52mm2 of silicon area with 15.8mW power consumption. The fabricated chip area and the measured power dissipation are reduced by 30% and 25% over conventional ones, respectively.
AB - While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the Alpha-Power Law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockley's square model. In this paper, we describe a 6-b 100MSPS CMOS current steering Digital-to-Analog Converter (DAC) with the Alpha-Power Law model. In order to improve the matching characteristics of the DAC current cell, moreover, we introduce a new and unique adaptive-control- switch (ACS) and a common current cell layout technique using a tournament algorithm. The prototype circuit has been fabricated with a Samsung 1.8V, 0.18μm, 1-poly, 5-metal CMOS technology. It occupies 0.52mm2 of silicon area with 15.8mW power consumption. The fabricated chip area and the measured power dissipation are reduced by 30% and 25% over conventional ones, respectively.
UR - http://www.scopus.com/inward/record.url?scp=57849111054&partnerID=8YFLogxK
U2 - 10.1109/ICECS.2008.4674840
DO - 10.1109/ICECS.2008.4674840
M3 - Conference contribution
AN - SCOPUS:57849111054
SN - 9781424421824
T3 - Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
SP - 259
EP - 262
BT - Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
T2 - 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Y2 - 31 August 2008 through 3 September 2008
ER -