TY - GEN
T1 - Design of a small-area Current Steering CMOS D/A converter based on a novel layout technique
AU - Minkyu, Song
PY - 2007
Y1 - 2007
N2 - A 12-b 300MSPS Current-Steering DAC with 0.13um CMOS technology is presented. In order to reduce the chip area, a laminated-step layout technique is proposed. Based on this technique, the occupied DAC core size is only 0.26mm2 even in 12-b resolution. Further, a current auto-averaging technique, an output impedance enhancement circuit, and the novel latched switching cell logic are discussed to keep the desired 12-b DAC performance. The measured results are within ±1LSB for DNL. The measured SFDR is 70dB under Nyquist output frequency with 50mW power dissipation at 3.3V power supply.
AB - A 12-b 300MSPS Current-Steering DAC with 0.13um CMOS technology is presented. In order to reduce the chip area, a laminated-step layout technique is proposed. Based on this technique, the occupied DAC core size is only 0.26mm2 even in 12-b resolution. Further, a current auto-averaging technique, an output impedance enhancement circuit, and the novel latched switching cell logic are discussed to keep the desired 12-b DAC performance. The measured results are within ±1LSB for DNL. The measured SFDR is 70dB under Nyquist output frequency with 50mW power dissipation at 3.3V power supply.
UR - http://www.scopus.com/inward/record.url?scp=48349145299&partnerID=8YFLogxK
U2 - 10.1109/ICASIC.2007.4415620
DO - 10.1109/ICASIC.2007.4415620
M3 - Conference contribution
AN - SCOPUS:48349145299
SN - 1424411327
SN - 9781424411320
T3 - ASICON 2007 - 2007 7th International Conference on ASIC Proceeding
SP - 273
EP - 276
BT - ASICON 2007 - 2007 7th International Conference on ASIC Proceeding
T2 - 2007 7th International Conference on ASIC, ASICON 2007
Y2 - 26 October 2007 through 29 October 2007
ER -