Design of an 8-bit 100 KSPS 1 mW CMOS A/D converter for digital mobile communication

Jungeun Lee; Minkyu Song

doi:10.1109/APASIC.1999.824058

Design of an 8-bit 100 KSPS 1 mW CMOS A/D converter for digital mobile communication

Jungeun Lee
, Minkyu Song

Division of System Semiconductor

Dongguk University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

In this paper, an 8-bit 100 KSPS 1 mW CMOS A/D converter for digital mobile communication is proposed. The main architecture of the A/D converter is based on a cyclic type, in order to reduce power consumption. This is composed of a proposed Sample and Hold Amplifier (SHA), fully differential gain amplifier and comparator. As the proposed SHA is driven by an offset cancellation clock to reduce offset voltage, the input voltage is held accurately. The proposed fully differential gain amplifier employs a half magnitude of the input capacitance compared to that of the conventional one. Thus both the input capacitance and feedback capacitance have the same value. The A/D converter is fabricated with a 0.6 μm single-poly triple-metal n-well CMOS technology and has a power consumption of 980 μW at 3 V power supply. Further, the INL and DNL are within ±1 LSB and SNR is about 45 dB.

Original language	English
Title of host publication	AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	178-185
Number of pages	8
ISBN (Print)	0780357051, 9780780357051
DOIs	https://doi.org/10.1109/APASIC.1999.824058
State	Published - 1999
Event	1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of Duration: 23 Aug 1999 → 25 Aug 1999

Publication series

Name	AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Conference

Conference	1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
Country/Territory	Korea, Republic of
City	Seoul
Period	23/08/99 → 25/08/99

Access to Document

10.1109/APASIC.1999.824058

Cite this

@inproceedings{34d36a7c9288473e9aaaa7c033d17fa0,

title = "Design of an 8-bit 100 KSPS 1 mW CMOS A/D converter for digital mobile communication",

abstract = "In this paper, an 8-bit 100 KSPS 1 mW CMOS A/D converter for digital mobile communication is proposed. The main architecture of the A/D converter is based on a cyclic type, in order to reduce power consumption. This is composed of a proposed Sample and Hold Amplifier (SHA), fully differential gain amplifier and comparator. As the proposed SHA is driven by an offset cancellation clock to reduce offset voltage, the input voltage is held accurately. The proposed fully differential gain amplifier employs a half magnitude of the input capacitance compared to that of the conventional one. Thus both the input capacitance and feedback capacitance have the same value. The A/D converter is fabricated with a 0.6 μm single-poly triple-metal n-well CMOS technology and has a power consumption of 980 μW at 3 V power supply. Further, the INL and DNL are within ±1 LSB and SNR is about 45 dB.",

author = "Jungeun Lee and Minkyu Song",

note = "Publisher Copyright: {\textcopyright} 1999 IEEE.; 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 ; Conference date: 23-08-1999 Through 25-08-1999",

year = "1999",

doi = "10.1109/APASIC.1999.824058",

language = "English",

isbn = "0780357051",

series = "AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "178--185",

booktitle = "AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs",

address = "United States",

}

Lee, J & Song, M 1999, Design of an 8-bit 100 KSPS 1 mW CMOS A/D converter for digital mobile communication. in AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs., 824058, AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs, Institute of Electrical and Electronics Engineers Inc., pp. 178-185, 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999, Seoul, Korea, Republic of, 23/08/99. https://doi.org/10.1109/APASIC.1999.824058

Design of an 8-bit 100 KSPS 1 mW CMOS A/D converter for digital mobile communication. / Lee, Jungeun; Song, Minkyu.
AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs. Institute of Electrical and Electronics Engineers Inc., 1999. p. 178-185 824058 (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - In this paper, an 8-bit 100 KSPS 1 mW CMOS A/D converter for digital mobile communication is proposed. The main architecture of the A/D converter is based on a cyclic type, in order to reduce power consumption. This is composed of a proposed Sample and Hold Amplifier (SHA), fully differential gain amplifier and comparator. As the proposed SHA is driven by an offset cancellation clock to reduce offset voltage, the input voltage is held accurately. The proposed fully differential gain amplifier employs a half magnitude of the input capacitance compared to that of the conventional one. Thus both the input capacitance and feedback capacitance have the same value. The A/D converter is fabricated with a 0.6 μm single-poly triple-metal n-well CMOS technology and has a power consumption of 980 μW at 3 V power supply. Further, the INL and DNL are within ±1 LSB and SNR is about 45 dB.

AB - In this paper, an 8-bit 100 KSPS 1 mW CMOS A/D converter for digital mobile communication is proposed. The main architecture of the A/D converter is based on a cyclic type, in order to reduce power consumption. This is composed of a proposed Sample and Hold Amplifier (SHA), fully differential gain amplifier and comparator. As the proposed SHA is driven by an offset cancellation clock to reduce offset voltage, the input voltage is held accurately. The proposed fully differential gain amplifier employs a half magnitude of the input capacitance compared to that of the conventional one. Thus both the input capacitance and feedback capacitance have the same value. The A/D converter is fabricated with a 0.6 μm single-poly triple-metal n-well CMOS technology and has a power consumption of 980 μW at 3 V power supply. Further, the INL and DNL are within ±1 LSB and SNR is about 45 dB.

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M3 - Conference contribution

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BT - AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999

Y2 - 23 August 1999 through 25 August 1999

ER -

Design of an 8-bit 100 KSPS 1 mW CMOS A/D converter for digital mobile communication

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