Design of an Asynchronous Detector with Priority Encoding Technique

Keunyeol Park; Ohoon Kwon; Hyunseob Noh; Minhyun Jin; Minkyu Song

doi:10.1109/ISVLSI.2017.98

Design of an Asynchronous Detector with Priority Encoding Technique

Keunyeol Park, Ohoon Kwon, Hyunseob Noh, Minhyun Jin, Minkyu Song

Division of System Semiconductor

Dongguk University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents an asynchronous detector with priority encoding technique. Conventionally, a normal synchronous detector like an image sensor checks all the outputs of detection cells, whatever the cells are activated or not. Thus, it spends a lot of undesired power consumption. On the contrary, an asynchronous detector to only check the activated cells has a small power consumption, even though it has a low operating speed. In order to improve the data transfer rates, a priority encoding technique is described. A test chip to verify the proposed technique has fabricated with 3.3V 0.18um 1-poly 5-metal CMOS process. The effective chip area is 0.345 mm2 and power consumption is about 8mW. The measured performance shows 65,026 patterns.

Original language	English
Title of host publication	Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
Editors	Ricardo Reis, Mircea Stan, Michael Huebner, Nikolaos Voros
Publisher	IEEE Computer Society
Pages	529-532
Number of pages	4
ISBN (Electronic)	9781509067626
DOIs	https://doi.org/10.1109/ISVLSI.2017.98
State	Published - 20 Jul 2017
Event	2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 - Bochum, North Rhine-Westfalia, Germany Duration: 3 Jul 2017 → 5 Jul 2017

Publication series

Name	Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Volume	2017-July
ISSN (Print)	2159-3469
ISSN (Electronic)	2159-3477

Conference

Conference	2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
Country/Territory	Germany
City	Bochum, North Rhine-Westfalia
Period	3/07/17 → 5/07/17

Keywords

asynchronous detector
CMOS process
priority encoding technique

Access to Document

10.1109/ISVLSI.2017.98

Cite this

Park, K., Kwon, O., Noh, H., Jin, M., & Song, M. (2017). Design of an Asynchronous Detector with Priority Encoding Technique. In R. Reis, M. Stan, M. Huebner, & N. Voros (Eds.), Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017 (pp. 529-532). Article 7987574 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2017-July). IEEE Computer Society. https://doi.org/10.1109/ISVLSI.2017.98

Park, Keunyeol ; Kwon, Ohoon ; Noh, Hyunseob et al. / Design of an Asynchronous Detector with Priority Encoding Technique. Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. editor / Ricardo Reis ; Mircea Stan ; Michael Huebner ; Nikolaos Voros. IEEE Computer Society, 2017. pp. 529-532 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI).

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title = "Design of an Asynchronous Detector with Priority Encoding Technique",

abstract = "This paper presents an asynchronous detector with priority encoding technique. Conventionally, a normal synchronous detector like an image sensor checks all the outputs of detection cells, whatever the cells are activated or not. Thus, it spends a lot of undesired power consumption. On the contrary, an asynchronous detector to only check the activated cells has a small power consumption, even though it has a low operating speed. In order to improve the data transfer rates, a priority encoding technique is described. A test chip to verify the proposed technique has fabricated with 3.3V 0.18um 1-poly 5-metal CMOS process. The effective chip area is 0.345 mm2 and power consumption is about 8mW. The measured performance shows 65,026 patterns.",

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Park, K, Kwon, O, Noh, H, Jin, M & Song, M 2017, Design of an Asynchronous Detector with Priority Encoding Technique. in R Reis, M Stan, M Huebner & N Voros (eds), Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017., 7987574, Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, vol. 2017-July, IEEE Computer Society, pp. 529-532, 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017, Bochum, North Rhine-Westfalia, Germany, 3/07/17. https://doi.org/10.1109/ISVLSI.2017.98

Design of an Asynchronous Detector with Priority Encoding Technique. / Park, Keunyeol; Kwon, Ohoon; Noh, Hyunseob et al.
Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. ed. / Ricardo Reis; Mircea Stan; Michael Huebner; Nikolaos Voros. IEEE Computer Society, 2017. p. 529-532 7987574 (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI; Vol. 2017-July).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper presents an asynchronous detector with priority encoding technique. Conventionally, a normal synchronous detector like an image sensor checks all the outputs of detection cells, whatever the cells are activated or not. Thus, it spends a lot of undesired power consumption. On the contrary, an asynchronous detector to only check the activated cells has a small power consumption, even though it has a low operating speed. In order to improve the data transfer rates, a priority encoding technique is described. A test chip to verify the proposed technique has fabricated with 3.3V 0.18um 1-poly 5-metal CMOS process. The effective chip area is 0.345 mm2 and power consumption is about 8mW. The measured performance shows 65,026 patterns.

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Park K, Kwon O, Noh H, Jin M, Song M. Design of an Asynchronous Detector with Priority Encoding Technique. In Reis R, Stan M, Huebner M, Voros N, editors, Proceedings - 2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017. IEEE Computer Society. 2017. p. 529-532. 7987574. (Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI). doi: 10.1109/ISVLSI.2017.98

Design of an Asynchronous Detector with Priority Encoding Technique

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Keywords

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