Design of low power digital VLSI circuits based on a novel pass-transistor logic

In this paper, a novel pass-transistor logic with an efficient level restoration circuit, named Power Saved Passtransistor Logic(PSPL), is proposed. It is shown how, through the use of regenerative feedback with pMOS switches, we reduce the power consumption and propagation delay compared to conventional pass-transistor logic. To demonstrate the performance of PSPL, a 54X 54-bit multiplier is designed. For speed and power optimization, the multiplier uses high compressionrate compressors without Booth Encoding, and a 108-bit conditional sum adder with separated carry generation block. The measured multiplication time was 13.5 ns in a 0.6 βm single-poly triple-metal 3.3 V CMOS process. Furthermore, a sequential circuit of a low power 7-bit serial counter is designed and fabricated in a 0.6 //m single-poly triple-metal 3.3 V CMOS process. The measured operating speed was 250 MHz.