Design of novel macro-cells for next generation ASIC cell library

Kiseon Cho, Minkyu Song

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper describes a design methodology of novel macro-cells for next generation ASIC libraries that has a low-power consumption and high-speed operation. In order to satisfy the desired characteristics, novel architectures of adder, multiplier, and shifter are proposed. Further, automatic layout generation programs are proposed. They are designed on the basis of the standard-cell approach, and they generate the layouts of the proposed macro-cells from 8-bit to 64-bit. The proposed macro-cells are designed with a novel compound logic that consists of both CMOS logic and pass-transistor logic. They are fabricated with 0.25um 1-poly 5-metal CMOS process, and have desired experimental results.

Original languageEnglish
Title of host publicationICECS 2000 - 7th IEEE International Conference on Electronics, Circuits and Systems
Pages320-323
Number of pages4
DOIs
StatePublished - 2000
Event7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000 - Jounieh, Lebanon
Duration: 17 Dec 200020 Dec 2000

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume1

Conference

Conference7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000
Country/TerritoryLebanon
CityJounieh
Period17/12/0020/12/00

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