Design of switching-mode CMOS frequency multipliers in sub-Terahertz regime

Jung Dong Park, Jung Dong Park

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

Switching mode CMOS frequency multipliers are studied in sub- Terahertz regime. Analysis on the multiplier architectures and optimal gate bias at CMOS switch are investigated to maximize output power at designated harmonics. Utilizing a differential pair, a 195 GHz tripler having a hairpin filter is designed to maximize 3rd harmonics with -14.8 dB of conversion gain (CG) from Pin = +13dBm of the balanced input, while the 260GHz quadrupler utilizes quadruple-push pairs which achieves CG = -16 dB from two +13dBm of the balanced I/Q driving signals in a 65 nm digital CMOS process.

Original languageEnglish
Article number20140806
JournalIEICE Electronics Express
Volume11
Issue number18
DOIs
StatePublished - 3 Sep 2014

Keywords

  • CMOS
  • Multiplier
  • Quadrupler
  • Sub-Terahertz
  • Tripler

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