Abstract
Switching mode CMOS frequency multipliers are studied in sub- Terahertz regime. Analysis on the multiplier architectures and optimal gate bias at CMOS switch are investigated to maximize output power at designated harmonics. Utilizing a differential pair, a 195 GHz tripler having a hairpin filter is designed to maximize 3rd harmonics with -14.8 dB of conversion gain (CG) from Pin = +13dBm of the balanced input, while the 260GHz quadrupler utilizes quadruple-push pairs which achieves CG = -16 dB from two +13dBm of the balanced I/Q driving signals in a 65 nm digital CMOS process.
Original language | English |
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Article number | 20140806 |
Journal | IEICE Electronics Express |
Volume | 11 |
Issue number | 18 |
DOIs | |
State | Published - 3 Sep 2014 |
Keywords
- CMOS
- Multiplier
- Quadrupler
- Sub-Terahertz
- Tripler