Device Temperature Reduction Methodology with a New Layout Drawing Technique for Ultra-thin FET

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Abstract

Conventionally, conductive material stacks composed of many metals and holes on silicon devices have kept excellent thermal paths which reduces junction temperature. However, according to the development of CMOS process technology, parasitic capacitance are also rapidly increasing and the thermal paths are also degrading. Thus, many ultra-thin FETs (Field Effect Transistor) are recently suffering from high temperature device problems. In this paper, device temperature reduction methodology with a new layout drawing technique is proposed for ultra-thin CMOS FETs. To verify the proposed new layout drawing technique, the secondary effects of various thermal paths with different metal stacks on junction temperature are analyzed, in terms of power consumption, oscillation frequency of ring oscillators, and etc. From the measured results of the oscillators, it is shown that the best heat-path design has about a 20%-lower change in junction temperature and a 1.5% higher oscillation frequency, compared to the conventional layouts. Furthermore, it is also shown that the proposed layout technique should be more effective with the ultra-thin FETs process rather than with the planar CMOS process.

Original languageEnglish
Title of host publicationTENSYMP 2021 - 2021 IEEE Region 10 Symposium
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665400268
DOIs
StatePublished - 23 Aug 2021
Event2021 IEEE Region 10 Symposium, TENSYMP 2021 - Jeju, Korea, Republic of
Duration: 23 Aug 202125 Aug 2021

Publication series

NameTENSYMP 2021 - 2021 IEEE Region 10 Symposium

Conference

Conference2021 IEEE Region 10 Symposium, TENSYMP 2021
Country/TerritoryKorea, Republic of
CityJeju
Period23/08/2125/08/21

Keywords

  • device temperature reduction methodology
  • metal stacks and holes
  • new layout drawing technique
  • thermal paths
  • ultra-thin FET

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