TY - GEN
T1 - Device Temperature Reduction Methodology with a New Layout Drawing Technique for Ultra-thin FET
AU - Jin, Minhyun
AU - Kim, Soo Youn
AU - Song, Minkyu
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021/8/23
Y1 - 2021/8/23
N2 - Conventionally, conductive material stacks composed of many metals and holes on silicon devices have kept excellent thermal paths which reduces junction temperature. However, according to the development of CMOS process technology, parasitic capacitance are also rapidly increasing and the thermal paths are also degrading. Thus, many ultra-thin FETs (Field Effect Transistor) are recently suffering from high temperature device problems. In this paper, device temperature reduction methodology with a new layout drawing technique is proposed for ultra-thin CMOS FETs. To verify the proposed new layout drawing technique, the secondary effects of various thermal paths with different metal stacks on junction temperature are analyzed, in terms of power consumption, oscillation frequency of ring oscillators, and etc. From the measured results of the oscillators, it is shown that the best heat-path design has about a 20%-lower change in junction temperature and a 1.5% higher oscillation frequency, compared to the conventional layouts. Furthermore, it is also shown that the proposed layout technique should be more effective with the ultra-thin FETs process rather than with the planar CMOS process.
AB - Conventionally, conductive material stacks composed of many metals and holes on silicon devices have kept excellent thermal paths which reduces junction temperature. However, according to the development of CMOS process technology, parasitic capacitance are also rapidly increasing and the thermal paths are also degrading. Thus, many ultra-thin FETs (Field Effect Transistor) are recently suffering from high temperature device problems. In this paper, device temperature reduction methodology with a new layout drawing technique is proposed for ultra-thin CMOS FETs. To verify the proposed new layout drawing technique, the secondary effects of various thermal paths with different metal stacks on junction temperature are analyzed, in terms of power consumption, oscillation frequency of ring oscillators, and etc. From the measured results of the oscillators, it is shown that the best heat-path design has about a 20%-lower change in junction temperature and a 1.5% higher oscillation frequency, compared to the conventional layouts. Furthermore, it is also shown that the proposed layout technique should be more effective with the ultra-thin FETs process rather than with the planar CMOS process.
KW - device temperature reduction methodology
KW - metal stacks and holes
KW - new layout drawing technique
KW - thermal paths
KW - ultra-thin FET
UR - http://www.scopus.com/inward/record.url?scp=85117489799&partnerID=8YFLogxK
U2 - 10.1109/TENSYMP52854.2021.9550978
DO - 10.1109/TENSYMP52854.2021.9550978
M3 - Conference contribution
AN - SCOPUS:85117489799
T3 - TENSYMP 2021 - 2021 IEEE Region 10 Symposium
BT - TENSYMP 2021 - 2021 IEEE Region 10 Symposium
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2021 IEEE Region 10 Symposium, TENSYMP 2021
Y2 - 23 August 2021 through 25 August 2021
ER -