Digital frequency modulation profile for low jitter spread spectrum clock generator

S. Byun, C. H. Son

Research output: Contribution to journalArticlepeer-review

Abstract

A new digital frequency modulation profile is presented for the design of a low jitter spread spectrum clock generator (SSCG). By using this proposed frequency modulation profile, the clock jitter due to frequency modulation can be significantly reduced. Simulation shows that the jitter is reduced from 0.29 to 0.065UI if the proposed frequency modulation profile is adopted. For the simulation, a 40-90 MHz SSCG with 1% of modulation ratio and 500 kHz of modulation frequency was designed in a 0.18 μm 1P4M CMOS process.

Original languageEnglish
Pages (from-to)1108-1110
Number of pages3
JournalElectronics Letters
Volume46
Issue number16
DOIs
StatePublished - 5 Aug 2010

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