Effects of the Process Variable on Sputtered TiSL_x Polycide Gate Electrodes for sub-0.15 μm Memory Device Application

We examine effects of the process variables of TiSi_x/poly-Si/oxide/Si transistor gate structures on material and electrical properties of TiSi_x films and patterned polycide gate lines at sub-0.15 μm regime. The process variables include molar ratio of Si/Ti in composite TiSi_x targets (x = 2.1, 2.2, 2.3, and 2.4), sputter deposition temperature, film thickness, rapid thermal annealing (RTA) process condition, and postannealing in a furnace. At high x (x ≥ 2.3). Si precipitate formation is highly pronounced at the film surface as RTA temperature increases and contributes to the increase in surface roughness of the films. Moreover, processes of higher A targets show a greater number of add-on particles and more retarded C54-TiSi₂ phase transformation. The RTA process after film deposition completely transforms TiSi_x (x = 2.1 ∼ 2.4) films to C54-TiSi₂ phase even at very fine lines when annealed at 800°C or higher for 20 s. The maximum thermal budget allowed for TiSi_x postannealing is 800°C for 60 min, where no appreciable thermal degradation is shown in bar resistance regardless of target composition. Al this postannealing condition, excellent bar resistance (∼4.4 Ω/□) and thermal stability are shown at 0.12 μm linewidth when TiSi_2.1 films were sputtered at 200°C. TiSi_2.1 films sputtered at 500°C show a stronger (040) C54 preferred orientation and greater degraded thermal stability than the films deposited at 200°C, and exhibit a bar resistance of ∼5 Ω/□ at 0.12 μm linewidth.