Electronic structure of pentacene/ultrathin gate dielectric interfaces for low-voltage organic thin film transistors

This paper describes the fabrication of pentacene-based thin film transistors (TFTs) with ultrathin (4.5 nm) Si O2 and SiON gate dielectric layers for low-voltage operations. The device with the SiON gate dielectric layer operated at gate voltages lower than -3.0 V, showing a threshold voltage of -0.45 V, which was lower than the threshold voltage of the Si O2 device (-2.5 V). The electronic structures of the interface between the pentacene and dielectric layers were investigated by in situ ultraviolet photoelectron spectroscopy (UPS) and x-ray photoelectron spectroscopy (XPS) to determine the reason for the lower operating voltage. The UPS and XPS results demonstrated that the interface dipole modified the potential of the dielectric layer, explaining the lower operating voltage. The electronic structure allowed for band bending at the interface, resulting in complete energy level diagrams for pentacene on Si O2 and SiON. The shifts in the threshold and turn-on voltages were explained by the energy level diagrams.