TY - GEN
T1 - Framework for simulation of the Verilog/SPICE mixed model
T2 - 2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014
AU - Seok, Moon Gi
AU - Park, Dae Jin
AU - Cho, Geun Rae
AU - Kim, Tag Gon
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2015/1/7
Y1 - 2015/1/7
N2 - Designing a mixed-signal integrated hardware requires the mixed simulation for legacy digital blocks and analog circuits, which are usually represented by the Verilog description language for digital blocks and the SPICE circuit netlist of analog circuits. Without model translations or source-level modifications and to simulate mixed legacy Verilog models and SPICE circuit netlists that are usually developed based on the different SPICE languages, parameters and primitives, this paper proposes a simulation framework whose concept is connecting a legacy Verilog and proper SPICE simulator for the target SPICE model using a run-time infrastructure (RTI) based on high level architecture (HLA) and adapters that are pluggable libraries to enable the interoperation and integration of simulators through HLA. For the interoperation, to exchange analog/digital signals, the adapter converts analog/digital signals to events or events to analog/digital signals using user-defined, signal-event converters. To synchronize different time advance policies, the adapter performs time synchronization procedures based on the pre-simulation concept. For the integration of Verilog/SPICE simulators and the RTI, adapters are developed following each component interface, which are IEEE-std Verilog procedural interface, proposed SPICE procedural interface and IEEE-std HLA interface. The proposed framework was applied to the digitally controlled buck converter simulation.
AB - Designing a mixed-signal integrated hardware requires the mixed simulation for legacy digital blocks and analog circuits, which are usually represented by the Verilog description language for digital blocks and the SPICE circuit netlist of analog circuits. Without model translations or source-level modifications and to simulate mixed legacy Verilog models and SPICE circuit netlists that are usually developed based on the different SPICE languages, parameters and primitives, this paper proposes a simulation framework whose concept is connecting a legacy Verilog and proper SPICE simulator for the target SPICE model using a run-time infrastructure (RTI) based on high level architecture (HLA) and adapters that are pluggable libraries to enable the interoperation and integration of simulators through HLA. For the interoperation, to exchange analog/digital signals, the adapter converts analog/digital signals to events or events to analog/digital signals using user-defined, signal-event converters. To synchronize different time advance policies, the adapter performs time synchronization procedures based on the pre-simulation concept. For the integration of Verilog/SPICE simulators and the RTI, adapters are developed following each component interface, which are IEEE-std Verilog procedural interface, proposed SPICE procedural interface and IEEE-std HLA interface. The proposed framework was applied to the digitally controlled buck converter simulation.
UR - http://www.scopus.com/inward/record.url?scp=84936888689&partnerID=8YFLogxK
U2 - 10.1109/VLSI-SoC.2014.7004185
DO - 10.1109/VLSI-SoC.2014.7004185
M3 - Conference contribution
AN - SCOPUS:84936888689
T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
BT - 2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Conference Proceedings
A2 - Garcia, Lorena
PB - IEEE Computer Society
Y2 - 6 October 2014 through 8 October 2014
ER -