FSLRU: A page cache algorithm for mobile devices with hybrid memory architecture

Even though page cache layer of operating system enhances the performance of mobile devices by reducing the number of write requests issued to the underlying mobile storage, the mobile devices still suffer from the excessive write requests. This is because mobile applications frequently trigger synchronous writes with fsync() system call to guarantee the reliability of each application. Unfortunately, these synchronous writes significantly draw both performance and battery power of mobile devices. This paper proposes a novel page cache algorithm, called fsync-Aware LRU (FSLRU), that adopts hybrid memory architecture, which is composed of DRAM and emerging nonvolatile memory (NVM). In particular, the proposed algorithm is designed to overcome the negative performance effect of NVM writes, which is measured on a real board. In order to improve performance and energy efficiency of mobile devices, FSLRU integrates the durability function into page cache layer and provides atomic update operations that are necessary to support strong durability. For detailed performance analyses, the proposed algorithm is implemented on a trace-driven simulator and is evaluated on a real board by replaying the results of the simulator. The evaluation results clearly present that FSLRU outperforms the conventional LRU algorithm by up to 3.2 times under three real world workloads while reducing power consumption by up to 99%¹.