Hard-pad-based CMP of premetal dielectric planarization

In the fabrication of modern Si ultra-large-scaled integrated circuits containing the dynamic random access memory blocks, high performance chemical mechanical polishing (CMP) for the planarization of premetal dielectrics (PMDs) is strongly required. Results of conventional CMP processing using the stack-type pads show good within-wafer uniformity; however this process produces severe degradation in planarity, especially between center and edge areas of the cell blocks. In this work, we describe an approach to the optimized PMD planarization method using the hard-pad-based CMP process and achieve desirable wafer-scaled uniformity and within-die planarity, simultaneously. To analyze the performance of PMD planarization, we also introduce a simple model to extract parameters corresponding to the PMD planarization efficiency. By optimizing the consumables of the polishers, the hard pad-based process shows a comparable within-wafer uniformity and ∼1/3 of within-die variation compared to the stack-type pad process.