TY - GEN
T1 - Identification of parameter domain for the design of high-speed I/O interface
AU - Kim, Seungwon
AU - Kim, Youngmin
AU - Han, Ki Jin
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2016/1/14
Y1 - 2016/1/14
N2 - To construct design rules for high-speed I/O interfaces, a method to identify the domain of design parameters for given electrical specifications is proposed in this paper. Since the shape of parameter domain is arbitrary and difficult to describe accurately, we simplify the problem by considering cubic domains only. Each domain is tested whether it belongs to the original parameter domain by Monte-Carlo sampling, and the volume of the domain is maximized by an optimization algorithm. During the procedure, computational burden due to a large number of samplings is addressed by reusing previously sampled data. By applying the developed method to a typical memory I/O interface model, we show the proposed approach can provide a practical and quantitative guideline for high-speed channel design.
AB - To construct design rules for high-speed I/O interfaces, a method to identify the domain of design parameters for given electrical specifications is proposed in this paper. Since the shape of parameter domain is arbitrary and difficult to describe accurately, we simplify the problem by considering cubic domains only. Each domain is tested whether it belongs to the original parameter domain by Monte-Carlo sampling, and the volume of the domain is maximized by an optimization algorithm. During the procedure, computational burden due to a large number of samplings is addressed by reusing previously sampled data. By applying the developed method to a typical memory I/O interface model, we show the proposed approach can provide a practical and quantitative guideline for high-speed channel design.
UR - http://www.scopus.com/inward/record.url?scp=84963860879&partnerID=8YFLogxK
U2 - 10.1109/EDAPS.2015.7383669
DO - 10.1109/EDAPS.2015.7383669
M3 - Conference contribution
AN - SCOPUS:84963860879
T3 - 2015 IEEE Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2015
SP - 67
EP - 70
BT - 2015 IEEE Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2015
Y2 - 14 December 2015 through 16 December 2015
ER -