Impact of drain induced barrier lowering on read scheme in silicon nanocrystal memory with two-bit-per-cell operation

Sangsu Park; Hyunsik Im; Ilgweon Kim; Toshiro Hiramoto

doi:10.1143/JJAP.45.638

Impact of drain induced barrier lowering on read scheme in silicon nanocrystal memory with two-bit-per-cell operation

Sangsu Park, Hyunsik Im, Ilgweon Kim, Toshiro Hiramoto

Division of System Semiconductor

Research output: Contribution to journal › Review article › peer-review

14 Scopus citations

Abstract

The threshold voltages (V_th's) and read schemes of silicon nanocrystal memories with two bits per cell are examined by experiments and simulations. It is found that the drain induced barrier lowering (DIBL) has a marked effect on V_th's in the four states and thus on read schemes for detecting the four V_th's. It is also shown that the read scheme can be selected by controlling DIBL using device parameters including gate length, injected charge fraction, and injected charge density. Suitable read schemes for low-voltage and low-power applications are discussed.

Original language	English
Pages (from-to)	638-642
Number of pages	5
Journal	Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume	45
Issue number	2 A
DOIs	https://doi.org/10.1143/JJAP.45.638
State	Published - 8 Feb 2006

Keywords

Drain induced barrier lowering (DIBL)
Low-voltage and low-power devices
Silicon nanocrystal
Threshold voltage

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10.1143/JJAP.45.638

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title = "Impact of drain induced barrier lowering on read scheme in silicon nanocrystal memory with two-bit-per-cell operation",

abstract = "The threshold voltages (Vth's) and read schemes of silicon nanocrystal memories with two bits per cell are examined by experiments and simulations. It is found that the drain induced barrier lowering (DIBL) has a marked effect on Vth's in the four states and thus on read schemes for detecting the four Vth's. It is also shown that the read scheme can be selected by controlling DIBL using device parameters including gate length, injected charge fraction, and injected charge density. Suitable read schemes for low-voltage and low-power applications are discussed.",

keywords = "Drain induced barrier lowering (DIBL), Low-voltage and low-power devices, Silicon nanocrystal, Threshold voltage",

author = "Sangsu Park and Hyunsik Im and Ilgweon Kim and Toshiro Hiramoto",

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Impact of drain induced barrier lowering on read scheme in silicon nanocrystal memory with two-bit-per-cell operation. / Park, Sangsu; Im, Hyunsik; Kim, Ilgweon et al.
In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol. 45, No. 2 A, 08.02.2006, p. 638-642.

Research output: Contribution to journal › Review article › peer-review

TY - JOUR

T1 - Impact of drain induced barrier lowering on read scheme in silicon nanocrystal memory with two-bit-per-cell operation

AU - Park, Sangsu

AU - Im, Hyunsik

AU - Kim, Ilgweon

AU - Hiramoto, Toshiro

PY - 2006/2/8

Y1 - 2006/2/8

N2 - The threshold voltages (Vth's) and read schemes of silicon nanocrystal memories with two bits per cell are examined by experiments and simulations. It is found that the drain induced barrier lowering (DIBL) has a marked effect on Vth's in the four states and thus on read schemes for detecting the four Vth's. It is also shown that the read scheme can be selected by controlling DIBL using device parameters including gate length, injected charge fraction, and injected charge density. Suitable read schemes for low-voltage and low-power applications are discussed.

AB - The threshold voltages (Vth's) and read schemes of silicon nanocrystal memories with two bits per cell are examined by experiments and simulations. It is found that the drain induced barrier lowering (DIBL) has a marked effect on Vth's in the four states and thus on read schemes for detecting the four Vth's. It is also shown that the read scheme can be selected by controlling DIBL using device parameters including gate length, injected charge fraction, and injected charge density. Suitable read schemes for low-voltage and low-power applications are discussed.

KW - Drain induced barrier lowering (DIBL)

KW - Low-voltage and low-power devices

KW - Silicon nanocrystal

KW - Threshold voltage

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EP - 642

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

IS - 2 A

ER -

Impact of drain induced barrier lowering on read scheme in silicon nanocrystal memory with two-bit-per-cell operation

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