Ladder-shaped network for ESD protection of millimetre-wave CMOS ICs

J. D. Park, A. M. Niknejad

Research output: Contribution to journalArticlepeer-review

6 Scopus citations

Abstract

A compact ladder-shaped electrostatic discharge (ESD) protection circuit is presented for millimetre-wave integrated circuits (ICs) in CMOS technology. Multiple shorted shunt stubs form a ladder network together with series stubs as ESD protection that discharges current/voltage pulses caused by an ESD event, while at the same time the network is embedded as part of the matching circuit for a normal operation. A 60GHz low-noise amplifier using a 90 nm CMOS process is demonstrated with the proposed ESD protection methodology that introduces less than 1dB insertion loss. Owing to the ESD current distribution through multiple shorted stubs, the proposed methodology is useful to millimetre-wave ICs with advanced CMOS technology that suffers from higher sheet resistance of the metal layers.

Original languageEnglish
Pages (from-to)795-797
Number of pages3
JournalElectronics Letters
Volume45
Issue number15
DOIs
StatePublished - 2009

Fingerprint

Dive into the research topics of 'Ladder-shaped network for ESD protection of millimetre-wave CMOS ICs'. Together they form a unique fingerprint.

Cite this