Abstract
We investigate the effects of liner scheme on the line and via resistances of aluminum damascene interconnects. The lowest line (∼0.19 Ω/sq. at 0.20 μm trench width) and via (∼0.5 Ω/via at 0.35 μm diameter) resistances are obtained at each different liner schemes of 30 nm TiN/20 nm Ti and 50 nm Ti-only, respectively. An optimized liner scheme of 10 nm TiN/40 nm Ti is therefore proposed. This scheme minimizes the TiAl3 formation due to the interfacial reaction between the Al and the TiN, and produces the most satisfactory resistances of the line (∼0.24 Ω/sq. at 0.2 μm trench width) and the via (∼0.9 Ω/via at 0.35 μm diameter), respectively.
Original language | English |
---|---|
Pages (from-to) | 1875-1879 |
Number of pages | 5 |
Journal | Solid-State Electronics |
Volume | 47 |
Issue number | 10 |
DOIs | |
State | Published - Oct 2003 |