Abstract
We examined the effects of the non-etchback passivation process using a low dielectric constant (εr) methylsilsesquioxane spin-on-glass (SOG) on the electrical characteristics of high-speed Si-based memory devices which are very sensitive to the parasitic coupling capacitance among the interconnection metal lines. The pass rate ratio of the fully functional on-wafer chips strongly depends on the dielectric constants, as well as on the local planarization, of SOG materials consisting of passivation structures deposited over the second metal lines. When low εr (∼2.7) methylsilsesquioxane SOG of a 6600 Å as-coated thickness is used for the passivation, a relative pass rate ratio of ∼92 % is obtained. This pass rate is almost comparable with the device yield of unpassivated chips (effective dielectric constant = 1) and is much higher than that (∼62 %) of chips passivated by using the conventional oxide/silicon-nitride structures. Compared to the conventional passivation structures, no significant shift in threshold voltage is observed in either active or field transistors with low εr SOG-based passivation structures, which suggests no electrical side effect on the metal-oxide-silicon transistors due to the methylsilsesquioxane SOG chemicals.
Original language | English |
---|---|
Pages (from-to) | 386-390 |
Number of pages | 5 |
Journal | Journal of the Korean Physical Society |
Volume | 43 |
Issue number | 3 |
State | Published - Sep 2003 |
Keywords
- CMOS
- Low-k
- Passivation
- SOG