Abstract
Memory management is one of the most important problem in implementing Viterbi decoders. This paper introduces a novel traceback scheme for memory management of high-speed Viterbi decoders. It is suitable for VLSI implementation since its address generation scheme for accessing memory contents is very simple and does not require global interconnection.
| Original language | English |
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| Pages | 511-520 |
| Number of pages | 10 |
| State | Published - 1995 |
| Event | Proceedings of the 1995 IEEE Workshop on VLSI Signal Processing - Osaka, Jpn Duration: 16 Oct 1995 → 18 Oct 1995 |
Conference
| Conference | Proceedings of the 1995 IEEE Workshop on VLSI Signal Processing |
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| City | Osaka, Jpn |
| Period | 16/10/95 → 18/10/95 |