TY - JOUR
T1 - More discussions on intrinsic frequency detection capability of full-rate linear phase detector in clock and data recovery
AU - Byun, Sangjin
N1 - Publisher Copyright:
© 2018 by the author. Licensee MDPI, Basel, Switzerland.
PY - 2018/6/8
Y1 - 2018/6/8
N2 - The full-rate linear phase detector (PD) has not only phase detection capability but also single-sided frequency detection capability intrinsically. Previously, this fact has been discovered by researching the phase and frequency characteristics of the combined full-rate linear PD and charge pump (CP) under the condition that the ratio of the received data frequency (fDATA) and the recovered clock frequency (fCLK) is set as an integer number. In this paper, for completeness of the theory, the phase and frequency characteristics of the combined full-rate linear PD and CP are studied again while the ratio of fDATA and fCLK is set as a general rational number. Additionally, theoretical analyses of the lock-in range and the lock time of the referenceless single-loop clock and data recovery (CDR) including the full-rate linear PD are newly developed and verified. The calculated lock times by the analysis results agree well with the measured lock times from the MATLAB Simulink simulations.
AB - The full-rate linear phase detector (PD) has not only phase detection capability but also single-sided frequency detection capability intrinsically. Previously, this fact has been discovered by researching the phase and frequency characteristics of the combined full-rate linear PD and charge pump (CP) under the condition that the ratio of the received data frequency (fDATA) and the recovered clock frequency (fCLK) is set as an integer number. In this paper, for completeness of the theory, the phase and frequency characteristics of the combined full-rate linear PD and CP are studied again while the ratio of fDATA and fCLK is set as a general rational number. Additionally, theoretical analyses of the lock-in range and the lock time of the referenceless single-loop clock and data recovery (CDR) including the full-rate linear PD are newly developed and verified. The calculated lock times by the analysis results agree well with the measured lock times from the MATLAB Simulink simulations.
KW - Clock and data recovery
KW - CMOS integrated circuits
KW - Frequency detection capability
KW - Linear phase detector
UR - http://www.scopus.com/inward/record.url?scp=85049540101&partnerID=8YFLogxK
U2 - 10.3390/electronics7060093
DO - 10.3390/electronics7060093
M3 - Article
AN - SCOPUS:85049540101
SN - 2079-9292
VL - 7
JO - Electronics (Switzerland)
JF - Electronics (Switzerland)
IS - 6
M1 - 93
ER -