On-cmos image sensor processing for lane detection

Soyeon Lee; Bohyeok Jeong; Keunyeol Park; Minkyu Song; Soo Youn Kim

doi:10.3390/s21113713

On-cmos image sensor processing for lane detection

Soyeon Lee, Bohyeok Jeong, Keunyeol Park, Minkyu Song, Soo Youn Kim

Division of System Semiconductor

Dongguk University

Research output: Contribution to journal › Article › peer-review

11 Scopus citations

Abstract

This paper presents a CMOS image sensor (CIS) with built-in lane detection computing circuits for automotive applications. We propose on-CIS processing with an edge detection mask used in the readout circuit of the conventional CIS structure for high-speed lane detection. Further-more, the edge detection mask can detect the edges of slanting lanes to improve accuracy. A prototype of the proposed CIS was fabricated using a 110 nm CIS process. It has an image resolution of 160 (H) × 120 (V) and a frame rate of 113, and it occupies an area of 5900 μm × 5240 μm. A comparison of its lane detection accuracy with that of existing edge detection algorithms shows that it achieves an acceptable accuracy. Moreover, the total power consumption of the proposed CIS is 9.7 mW at pixel, analog, and digital supply voltages of 3.3, 3.3, and 1.5 V, respectively.

Original language	English
Article number	3713
Journal	Sensors
Volume	21
Issue number	11
DOIs	https://doi.org/10.3390/s21113713
State	Published - 1 Jun 2021

Keywords

CMOS image sensor
Computer vision
Edge detection
Low power consumption
Single-slope ADC

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10.3390/s21113713

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title = "On-cmos image sensor processing for lane detection",

abstract = "This paper presents a CMOS image sensor (CIS) with built-in lane detection computing circuits for automotive applications. We propose on-CIS processing with an edge detection mask used in the readout circuit of the conventional CIS structure for high-speed lane detection. Further-more, the edge detection mask can detect the edges of slanting lanes to improve accuracy. A prototype of the proposed CIS was fabricated using a 110 nm CIS process. It has an image resolution of 160 (H) × 120 (V) and a frame rate of 113, and it occupies an area of 5900 μm × 5240 μm. A comparison of its lane detection accuracy with that of existing edge detection algorithms shows that it achieves an acceptable accuracy. Moreover, the total power consumption of the proposed CIS is 9.7 mW at pixel, analog, and digital supply voltages of 3.3, 3.3, and 1.5 V, respectively.",

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author = "Soyeon Lee and Bohyeok Jeong and Keunyeol Park and Minkyu Song and Kim, {Soo Youn}",

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AU - Lee, Soyeon

AU - Jeong, Bohyeok

AU - Park, Keunyeol

AU - Song, Minkyu

AU - Kim, Soo Youn

PY - 2021/6/1

Y1 - 2021/6/1

N2 - This paper presents a CMOS image sensor (CIS) with built-in lane detection computing circuits for automotive applications. We propose on-CIS processing with an edge detection mask used in the readout circuit of the conventional CIS structure for high-speed lane detection. Further-more, the edge detection mask can detect the edges of slanting lanes to improve accuracy. A prototype of the proposed CIS was fabricated using a 110 nm CIS process. It has an image resolution of 160 (H) × 120 (V) and a frame rate of 113, and it occupies an area of 5900 μm × 5240 μm. A comparison of its lane detection accuracy with that of existing edge detection algorithms shows that it achieves an acceptable accuracy. Moreover, the total power consumption of the proposed CIS is 9.7 mW at pixel, analog, and digital supply voltages of 3.3, 3.3, and 1.5 V, respectively.

AB - This paper presents a CMOS image sensor (CIS) with built-in lane detection computing circuits for automotive applications. We propose on-CIS processing with an edge detection mask used in the readout circuit of the conventional CIS structure for high-speed lane detection. Further-more, the edge detection mask can detect the edges of slanting lanes to improve accuracy. A prototype of the proposed CIS was fabricated using a 110 nm CIS process. It has an image resolution of 160 (H) × 120 (V) and a frame rate of 113, and it occupies an area of 5900 μm × 5240 μm. A comparison of its lane detection accuracy with that of existing edge detection algorithms shows that it achieves an acceptable accuracy. Moreover, the total power consumption of the proposed CIS is 9.7 mW at pixel, analog, and digital supply voltages of 3.3, 3.3, and 1.5 V, respectively.

KW - CMOS image sensor

KW - Computer vision

KW - Edge detection

KW - Low power consumption

KW - Single-slope ADC

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On-cmos image sensor processing for lane detection

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Keywords

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