TY - JOUR
T1 - Rigorous electrical modeling of through silicon vias (TSVs) with MOS capacitance effects
AU - Bandyopadhyay, Tapobrata
AU - Han, Ki Jin
AU - Chung, Daehyun
AU - Chatterjee, Ritwik
AU - Swaminathan, Madhavan
AU - Tummala, Rao
PY - 2011/6
Y1 - 2011/6
N2 - 3-D integration of microelectronic systems reduces the interconnect length, wiring delay, and system size, while enhancing functionality by heterogeneous integration. Through silicon via (TSV) is a key building block for high-performance 3-D systems. This paper presents an accurate electrical modeling of TSVs considering metal-oxide-semiconductor (MOS) capacitance effects. The model is correlated with measurement results for validation. Parametric analysis of TSV capacitance is performed on several physical and material parameters. Design guidelines are proposed for TSVs used in signal and power distribution networks as well as for TSVs as variable capacitors. A 3-D power distribution network is simulated to show the effect and importance of the voltage-dependent TSV MOS capacitance.
AB - 3-D integration of microelectronic systems reduces the interconnect length, wiring delay, and system size, while enhancing functionality by heterogeneous integration. Through silicon via (TSV) is a key building block for high-performance 3-D systems. This paper presents an accurate electrical modeling of TSVs considering metal-oxide-semiconductor (MOS) capacitance effects. The model is correlated with measurement results for validation. Parametric analysis of TSV capacitance is performed on several physical and material parameters. Design guidelines are proposed for TSVs used in signal and power distribution networks as well as for TSVs as variable capacitors. A 3-D power distribution network is simulated to show the effect and importance of the voltage-dependent TSV MOS capacitance.
KW - 3-D integration
KW - interconnection modeling
KW - parametric study
KW - power distribution network
KW - through silicon via
KW - variable capacitance
UR - http://www.scopus.com/inward/record.url?scp=84857454206&partnerID=8YFLogxK
U2 - 10.1109/TCPMT.2011.2120607
DO - 10.1109/TCPMT.2011.2120607
M3 - Article
AN - SCOPUS:84857454206
SN - 2156-3950
VL - 1
SP - 893
EP - 903
JO - IEEE Transactions on Components, Packaging and Manufacturing Technology
JF - IEEE Transactions on Components, Packaging and Manufacturing Technology
IS - 6
M1 - 5765485
ER -