RS-CIM: Area-efficient Compute-in-Memory with R-DAC & SAR Hybrid ADC

Kyu Hyun Lee; Minkyu Song; Soo Youn Kim

doi:10.1109/ISCAS56072.2025.11043303

RS-CIM: Area-efficient Compute-in-Memory with R-DAC & SAR Hybrid ADC

Kyu Hyun Lee
, Minkyu Song
, Soo Youn Kim

Division of System Semiconductor

Dongguk University

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Analog computing offers higher energy efficiency compared to digital, making it suitable for low-power applications. However, the area overhead of digital-to-analog converter (DAC) and analog-to-digital converter (ADC) reduces area efficiency, either by requiring an analog MUX or by lowering cell array density. To solve this problem, we propose a high-area efficiency analog compute-in-memory structure consisting of a 7T SRAM-based digital-to-time converter with clock multiplication and a hybrid ADC structure of a resistor-DAC and SAR ADC. Compared to conventional SAR ADCs and flash ADCs, the number of capacitors and comparators was reduced by 87.5% and 93.3%, respectively. As a result, we achieved 247.7 TOPS/W and 6.498 TOPS/mm² when scaling down to 28 nm process.

Original language	English
Title of host publication	ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350356830
DOIs	https://doi.org/10.1109/ISCAS56072.2025.11043303
State	Published - 2025
Event	2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 - London, United Kingdom Duration: 25 May 2025 → 28 May 2025

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025
Country/Territory	United Kingdom
City	London
Period	25/05/25 → 28/05/25

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

7T SRAM-based Digital-to-Time Converter(7TC)
8T compact SRAM
Analog Computing
Compute-in-Memory
R-DAC&SAR hybrid ADC(RS-ADC)

Access to Document

10.1109/ISCAS56072.2025.11043303

Cite this

@inproceedings{0494b9d96d814a3285c44df8f4584cce,

title = "RS-CIM: Area-efficient Compute-in-Memory with R-DAC \& SAR Hybrid ADC",

abstract = "Analog computing offers higher energy efficiency compared to digital, making it suitable for low-power applications. However, the area overhead of digital-to-analog converter (DAC) and analog-to-digital converter (ADC) reduces area efficiency, either by requiring an analog MUX or by lowering cell array density. To solve this problem, we propose a high-area efficiency analog compute-in-memory structure consisting of a 7T SRAM-based digital-to-time converter with clock multiplication and a hybrid ADC structure of a resistor-DAC and SAR ADC. Compared to conventional SAR ADCs and flash ADCs, the number of capacitors and comparators was reduced by 87.5\% and 93.3\%, respectively. As a result, we achieved 247.7 TOPS/W and 6.498 TOPS/mm2 when scaling down to 28 nm process.",

keywords = "7T SRAM-based Digital-to-Time Converter(7TC), 8T compact SRAM, Analog Computing, Compute-in-Memory, R-DAC\&SAR hybrid ADC(RS-ADC)",

author = "Lee, \{Kyu Hyun\} and Minkyu Song and Kim, \{Soo Youn\}",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 ; Conference date: 25-05-2025 Through 28-05-2025",

year = "2025",

doi = "10.1109/ISCAS56072.2025.11043303",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings",

address = "United States",

}

Lee, KH, Song, M & Kim, SY 2025, RS-CIM: Area-efficient Compute-in-Memory with R-DAC & SAR Hybrid ADC. in ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025, London, United Kingdom, 25/05/25. https://doi.org/10.1109/ISCAS56072.2025.11043303

RS-CIM: Area-efficient Compute-in-Memory with R-DAC & SAR Hybrid ADC. / Lee, Kyu Hyun; Song, Minkyu ; Kim, Soo Youn.
ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2025. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - RS-CIM

T2 - 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025

AU - Lee, Kyu Hyun

AU - Song, Minkyu

AU - Kim, Soo Youn

PY - 2025

Y1 - 2025

N2 - Analog computing offers higher energy efficiency compared to digital, making it suitable for low-power applications. However, the area overhead of digital-to-analog converter (DAC) and analog-to-digital converter (ADC) reduces area efficiency, either by requiring an analog MUX or by lowering cell array density. To solve this problem, we propose a high-area efficiency analog compute-in-memory structure consisting of a 7T SRAM-based digital-to-time converter with clock multiplication and a hybrid ADC structure of a resistor-DAC and SAR ADC. Compared to conventional SAR ADCs and flash ADCs, the number of capacitors and comparators was reduced by 87.5% and 93.3%, respectively. As a result, we achieved 247.7 TOPS/W and 6.498 TOPS/mm2 when scaling down to 28 nm process.

AB - Analog computing offers higher energy efficiency compared to digital, making it suitable for low-power applications. However, the area overhead of digital-to-analog converter (DAC) and analog-to-digital converter (ADC) reduces area efficiency, either by requiring an analog MUX or by lowering cell array density. To solve this problem, we propose a high-area efficiency analog compute-in-memory structure consisting of a 7T SRAM-based digital-to-time converter with clock multiplication and a hybrid ADC structure of a resistor-DAC and SAR ADC. Compared to conventional SAR ADCs and flash ADCs, the number of capacitors and comparators was reduced by 87.5% and 93.3%, respectively. As a result, we achieved 247.7 TOPS/W and 6.498 TOPS/mm2 when scaling down to 28 nm process.

KW - 7T SRAM-based Digital-to-Time Converter(7TC)

KW - 8T compact SRAM

KW - Analog Computing

KW - Compute-in-Memory

KW - R-DAC&SAR hybrid ADC(RS-ADC)

UR - https://www.scopus.com/pages/publications/105010624878

U2 - 10.1109/ISCAS56072.2025.11043303

DO - 10.1109/ISCAS56072.2025.11043303

M3 - Conference contribution

AN - SCOPUS:105010624878

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 25 May 2025 through 28 May 2025

ER -

RS-CIM: Area-efficient Compute-in-Memory with R-DAC & SAR Hybrid ADC

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

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