Scaled LTPS TFTs for low-cost low-power applications

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7 Scopus citations

Abstract

Low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs) have emerged as a promising technology for applications such as low-cost sensor networks. In this paper, we propose a LTPS TFT device optimization methodology based on scaling of silicon body (Tsi) and buried oxide thickness (Tbox). The proposed approach is applicable for both digital and analog circuits. Results show that using the proposed device we can achieve 133X improvement in oscillation frequency of a three-stage ring oscillator (RO) and 31% improvement in operational amplifier (OPAMP) gain (Tsi 10nm and Tbox 10nm) compared to the traditional device structures. We believe that proper optimization of TFT device geometry parameters is necessary to realize low-power, high-performance, and low-cost LTPTS TFT digital & analog/RF circuits.

Original languageEnglish
Title of host publicationProceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011
Pages745-750
Number of pages6
DOIs
StatePublished - 2011
Event12th International Symposium on Quality Electronic Design, ISQED 2011 - Santa Clara, CA, United States
Duration: 14 Mar 201116 Mar 2011

Publication series

NameProceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011

Conference

Conference12th International Symposium on Quality Electronic Design, ISQED 2011
Country/TerritoryUnited States
CitySanta Clara, CA
Period14/03/1116/03/11

Keywords

  • BOX (buried oxide)
  • Buried-oxide Induced Barrier Lowering (BIBL)
  • Drain Induced Barrier Lowering (DIBL)
  • Thin Film Transistor (TFT)

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