Statistical TDDB Degradation in Memory Circuits: Bit-Cells to Arrays

A physics-based SPICE model that takes into account the statistical impacts of both successive and progressive oxide breakdowns is presented to evaluate the time-dependent dielectric breakdown (TDDB)-induced performance degradation in static random access memory cells and peripheral circuits. The postbreakdown I-V characteristics and the distribution of time to breakdown (t_BD) have been verified against experimental data from 45-nm Silicon on insulator technology. We show that peripheral circuits, such as word-line driver, sense amplifier, and write driver, also contribute to degradation of performance during read and write operations. Using the model, the statistical impact of TDDB on sensing delay and write access time can be properly modeled for read and write failure prediction.