Stress-induced voiding in sputtered TiSi_x complementary metal oxide silicon gate electrodes

We examined the effect of shallow trench isolation (STI) process for the Si ultralarge-scaled integrated circuit on the thermal stability of the bar resistance (R_s) and the internal void formation of sputtered-TiSi₂/poly-Si gate electrodes. Among the examined process variables, the STI step height can strongly affect the density of voids formed between the poly-Si and the TiSi₂ films after the silicidation annealing. Above a STI step height of 400 Å, many clear voids were observed at the STI boundaries by scanning electron microscopy. The thermal stability of the sheet resistance (R_s) for the TiSi₂/poly-Si gate electrode was investigated at various STI step heights and Si/Ti molar ratios (x) of the TiSi_x composite target. With the decrease in STI step height from 400 to 200 Å, the average R_s at a 0.16 μm linewidth was enhanced from ∼60 to 15 Ω/□ after postannealing at 800°C for 2 h. With the increase of x from 2.1 to 2.3, the thermal stability of R_s was also greatly enhanced showing an average R_s of ∼15 Ω/□ at a 400 Å STI step height. From this study, we suggest that the stress-induced voiding at TiSi₂/poly-Si interface plays one of key roles in thermal degradation of R_s due to the highly developed triaxial stress state in the gate electrode film.