Abstract
This paper presents device models and optimization methodology for reducing short-channel effects in low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs), which are suitable for standard complementary metal-oxide-semiconductor (CMOS)-compatible analog operations. We analyze channel-length modulation to determine appropriate channel length having a single grain boundary in the channel fabricated using excimer laser-annealed crystallization under low-temperature constraint. Furthermore, buried-oxide-induced barrier lowering (BIBL) is investigated in poly-Si TFTs. BIBL makes the effective channel length shorter, resulting in difficulty to use LTPS TFTs for analog applications due to small output resistance r out. We show that, with scaling of the buried-oxide (BOX) thickness Tbox and an appropriate channel length, rout and the normalized transconductance gm/Id (with Tbox = 10 nm) can be improved by 103% and 8%, respectively, compared with thicker BOX (Tbox = 50 nm). In addition, due to the decrease in leakage currents, the Ion/Ioff ratio of the thin-BOX device can be three times larger than that of the thicker BOX device. Based on the process-constrained optimized device, we designed a 417-μW 65-dB folded-cascode operational amplifier with 2-V supply for CMOS-compatible operations.
Original language | English |
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Article number | 5742689 |
Pages (from-to) | 1687-1695 |
Number of pages | 9 |
Journal | IEEE Transactions on Electron Devices |
Volume | 58 |
Issue number | 6 |
DOIs | |
State | Published - Jun 2011 |
Keywords
- Buried-oxide (BOX)-induced barrier lowering (BIBL)
- channel-length modulation (CLM)
- low-temperature polycrystalline silicon (LTPS)
- operational amplifier (op amp)
- output resistance r
- thin-film transistor (TFT)
- transconductance g